By Raghu Shankar | LinkedIn, June 2026
Systems-in-package (SIPs) with 2.5D and 3D heterogenous integration, consisting of multiple dies and chiplets deliver 10x more functionality than traditional monolithic chips. This capability enables innovative solutions for diverse needs in scientific computing, automotive, edge computing, and aerospace/defense.
Chiplets deliver modular building blocks with smaller dies at higher yields thereby lowering costs. It also enables higher reusability across product lines and across generations. This approach has been adopted by established vendors, on proven legacy designs, in well-understood markets, and in closed eco-systems of few vendors. Beyond that, dies and chiplets can be available from wide range of organizations and generations. Many technologies and standards are in place to speed interoperability and adoption in multi-vendor eco-systems.
Despite the advantages of SIPs and chiplets, broad adoption across a wider range of market opportunities with lower volumes and at lower budgets remains a major challenge. There is a bottleneck right up-front during planning and design phase to identify promising ventures.
- First, the market need must be clearly defined, including the value proposition, solution adoption potential, price sensitivity, and demand profile.
- Second, each vendor across the supply chain must be confident that their investment will be profitable at level of manageable risk. Further each vendor wants to expand their pool of options to maximize their investments across multiple products, multiple buyers, and multiple generations.
Systematically evaluating the best combinations of design options on both technical merits and business case perspectives from a large pool of IP options improves profitability and spreads risk.
This is a 3-part problem to solve:
- Articulate value proposition to adopters on how the new solution is far superior to the prior ones factoring in the migration effort and risk.
- Estimate demand, i.e., market size, that is sizeable for supply side investments.
- Each vendor on the supply side needs to prove its profitability and prioritize with other competing investments.
The above needs to be solved in a low-risk, low cost, and low-friction manner for any one market opportunity. The evaluation methodology and its outcomes need to be generally agreed upon by the diverse stakeholders including potential adopters. Further this evaluation needs to be scaled to 1000’s of opportunities from which a handful will make the cut for further investigation and investment. To solve this front-end bottleneck, we need to reduce friction and lower barriers for multi-organization explorations.
This requires a shift-left: Shift multi-vendor evaluations as early as possible to the front-end of the design cycle. This is the planning phase, design space exploration, architecture design and power-performance, area and cost (PPAC) estimation phase for further investments.
This requires a shift-up: Scope it down to architecture layer for faster interoperability testing. Abstract up the architecture implications of the lower three layers (physical, adapter/link, and protocol). Starting at the architectural layer (pre-RTL) speeds up evaluations. It allows exploring many configurations that can be synthesized (via HLS) for PPAC estimates. Simulation, emulation, and prototyping may be used for higher confidence estimates.
This requires a shift-out: Break out of industry silos, expand the pool of buyers and sellers, expand the pool of IP for explorations. Maximize finding (or co-developing) the best fit in terms of PPAC for the solution.
Lastly, today a lot of time is spent on repetitive and mundane activities of searching for vendors, IP, specs, tools alignment, benchmarks and test selection, PPA compatibility, etc. before the first interoperability evaluations can be started.
As an industry we need to define a robust, AI native multi-vendor virtual chiplet eco-system for planning and prototyping phases. With security, governance, and safeguards in place, this virtual eco-system will include specs, proven behavioral models, curated stimuli, reference designs, interop verification methodologies, and interoperability results.
AI Native: Many aspects of AI available today and in the future must be applied extensively to exponentially increase early-stage explorations while reducing mundane and repetitive activities. AI native includes semantic and keyword search of specs, rank ordering and scoring top matches, highlighting gaps, code generation, connections to EDA tools, test benches, and benchmarks.
Incorporate best practices including encrypted models, containerized models, fast models, fixed virtual platforms, cloud, IP libraries, local and remote verification IP, STCO, and scenario-based modeling.
Humans will set the objectives and level of interop validation required with AI automating the process flows for the design space explorations via simulations, emulation, and prototyping.
Leaders shaping the vision
The industry needs to deliver on the advances of system in packages, heterogenous integration to solve many high impact needs in scientific computing, automotive, defense and more. They can be better addressed through multi-vendor, heterogenous solutions, mixing new IP and existing designs, lower power, cost, and maximizing memory utilization (valuable commodity now).
The leaders in the industry need to start the dialog today to shape this vision, call out the challenges, and overcome hurdles for this multi-year journey.
Open chiplet economy (OCE) under Open Compute Project (OCP) is a vendor-neutral body encouraging participation from commercial, research labs, and academia who benefit from this initiative. OCP/OCE amplifies this effort through summits, newsletters, webinars, and more to build more visibility for this vision.
More on how to shape the vision, visit https://www.opencompute.org/community/open-chiplet-economy/open-framework-for-chiplet-eco-system-virtual-prototyping
Also Read:
The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox, Daniel Nenni, Editor SemiWiki, May 2026
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools
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