Intel presented yesterday on their plans for process technology and packaging over the next several years. This was the most detailed roadmap Intel has ever laid out. In this write up I will analyze Intel’s process announcement and how they match up with their competitors.
10nm Super Fin (SF)
10nm is now in volume production in three… Read More
Ansys Multiphysics Platformby Tom Dillinger on 07-26-2021 at 10:00 amCategories: Ansys, Inc., EDA
Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications. Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More
80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
– Strong demand across logic/memory & leading/trailing edge
– Customers want units fast-no time to test
– The main question is can ASML ramp to meet demand?
Revenue & Earnings low due to systems being rushed to customers
ASML reported Euro 4B in sales and Euro 1B in net income which while within guidance… Read More
Dan is joined by Tony Pialis. Tony co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. The journey of Alphawave is discussed, including differentiation, strategy and the IPO as well as a look to the future.
Tony co-founded Alphawave in 2017 and has since served as its President and Chief… Read More
Architectural exploration is a vast area of engineering design. It starts with the planning phase where the designer will have the list of requirements from the customer and the rough architecture most likely on a paper. Next is to assemble the model and conduct variety of trade-offs for optimization and functional studies to … Read More
Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement… Read More
Previous SemiWiki articles have discussed the introduction of embedded Spin-Transfer Torque Magnetoresistive RAM IP from GLOBALFOUNDRIES, as an evolution replacement for non-volatile embedded flash memory. (link, link)
Those articles described the key features of STT-MRAM technology, but didn’t delve into a key reliability… Read More
Electronics production continues to recover from the COVID-19 pandemic. However, the recovery is mixed by country. The chart below shows three-month-average (3/12) change versus a year ago in electronics production by local currency for key Asian countries. China was averaging about 10% growth prior to the pandemic. After… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet