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Verifying 10+ Billion-Gate Designs Requires Distinct, Scalable Hardware Emulation Architecture

Verifying 10+ Billion-Gate Designs Requires Distinct, Scalable Hardware Emulation Architecture
by Daniel Nenni on 08-29-2022 at 6:00 am

960 x 540 Veloce

In a two-part series, Lauro Rizzatti examines why three kinds of hardware-assisted verification engines are a must have for today’s semiconductor designs. To do so, he interviewed Siemens EDA’s Vijay Chobisa and Juergen Jaeger to learn more about the Veloce hardware-assisted verification systems.

What follows is part one, a condensed version of his discussion with Vijay Chobisa,

Product Marketing Director in the Scalable Verification Solution division at Siemens EDA. They talk about why verification of 10+ billion-gate design requires a distinct architecture.

LR: The most recent announcement from Siemens EDA in the hardware-assisted verification area included an expansion of the capabilities of the Veloce Strato emulator with a new Veloce Strato+, Veloce Primo for enterprise prototyping, and Veloce proFPGA for desktop type prototyping. What has been the customer response to these new capabilities?

VC: Last year, we announced Veloce Strato+ emulation platform, Veloce Primo Enterprise prototyping system, and Veloce proFPGA traditional prototyping system. The response from our customers has been fantastic. Let me briefly go through what the new capabilities consist of.

When we announced Veloce Strato+, we specified the ability to emulate a single instance of an SoC design as big as 12-billion gates. Today, we have several customers emulating 10- to 12-billion gate designs on Strato+. Such designs are becoming popular in the areas of AI and machine learning, networking, CPUs/GPUs, and other leading-edge industries. What customers really like about Veloce Strato+ is the ability to move their entire verification environment from Veloce Strato by just flipping a single compile switch and get 1.5X capacity in same footprint.

A unique feature of Veloce Primo is the interoperability with Veloce Strato+. A customer owning both platforms can switch from emulation to prototyping when designs reach stability, to run at a much faster speed, and in the process get more verification cycles at lower cost. They can also switch back from prototyping to emulation when they run into a design bug and need to root cause the issue, correct the design and verify the issue has been removed. Veloce Strato+ excels in design turnaround time (TAT) by supporting 100% native visibility, like in simulation, with rapid waveform generation, as well as fast and reliable compilation.

Our Veloce proFPGA prototyping delivers ultra-high speed in the ballpark of 50-100 MHz to support software teams performing software validation.

LR: How do you describe the advantages of the Veloce platform approach and how it differs from other hardware assisted verification approaches?

VC: Let me start by saying that we are working very closely with our partner customers and we attentively monitor their roadmaps to make sure that we are providing verification and validation tools to address their challenges. Let me touch on some of those.

We have seen three common design trends across several industries. First, designs are becoming very large. Second, thorough verification and validation of such designs before tape out requires the execution of vast amount of software workloads, run different use cases. Third, power and performance have become critical. To deal with all of the above, we had to address three fundamental aspects of the Veloce platform: design capacity, design compilation, and design debug.

When I say that Veloce Strato+ can emulate a 12-billion gate design, that’s not by luck. We designed a unique architecture that can scale in all three aspects. Veloce Strato+ is a robust system that can map and emulate monolithic designs of up to 12-billion gates, executing large workloads for a very long time with reliability and repeatability.

The Veloce Strato+ compiler can map 12-billion gates designs in less than a full day. Customers would like to get a minimum of one or two turns a day in order to use emulation effectively for doing verification. Our compiler takes advantage of design structures assembled by customers and advancements in processor/server topology. We developed technologies called template processing, distributed Velsyn, and technology like ECO compile. Our goal is to allow users to perform a couple of compilations per day, even for very large designs.

The final aspect is design debug. Customers coming from simulation would like to see exactly the same debugging environment in emulation just running faster at larger scale. We support the same Visualizer GUI across simulation, emulation and prototyping.

A unique differentiator of the Veloce architecture is fast waveform generation regardless of the design size. For example, Veloce can capture the data for every node in the design for one-million cycles and generate waveforms within five minutes, regardless of the design size. Whether the design is half a billion gates or four-billion gates or 12-billion gates, the time to generate the entire set of waveforms for one-million cycles is the same.

The bottom line is that the Strato+ architecture scales not only in terms of capacity, but also in terms of infrastructure to provide an efficient environment for compiling, running and debugging large designs, rapidly, accurately, and reliably. Users can run emulation, find a bug, fix the design and validate the change all within a day.

All of the above are advantages of Veloce Strato+ vis-à-vis our competition. As of today, Strato+4M is the only emulator on the market that can emulate 10- to 12-billion gates monolithic designs efficiently and consistently.

LR: Let’s look into the future. What are you hearing from customers and potential Veloce users about additional challenges and needs for hardware assistive verification tools for the next three years?

VC: As I mentioned, we work closely with our customers to design better hardware-assisted verification products that meet customer requirements. Let me give you some examples of how we solve customer issues.

Traditionally emulation in the storage market is used in in-circuit-emulation (ICE) mode where the design is connected to and driven by physical devices. This use mode is inherently limited when it comes to measuring bandwidth or I/O traffic performance, debug and access by teams from different geographies.

Instead, we built a solution based on virtual devices in close collaboration with top storage customers. We have many customers using Veloce to verify their design and software by using ICE setups. However, our customers are adopting more and more a VirtuaLAB-based use model due to the above changes with ICE. Today, storage customers using Veloce Strato+, can do exactly what they were doing in the ICE environment plus measure very accurately I/O bandwidth traffic and error injection to test corner case scenarios. They can also perform power analysis, a critical objective in the storage industry.

Our approach is to work with customers in each vertical market segment to understand their challenges and build an efficient and effective solution.

As already mentioned, power and performance are becoming critical not only for customers designing smart devices, but also for semiconductors powering up HPC and data centers. Again, we work closely with these customers to allow the “shift-left” in power profiling, power analysis, and to generate accurate power numbers by running software applications, customer workload and benchmarks. This early power proofing allows them to impact RTL code and software to ensure that their power budget is within the envelop and also that they can deliver the required performance.

Another aspect is functional safety. In some market segments today, functional safety is becoming very important. People designing autonomous cars or chips in the mil-aero industry consider functional safety verification a critical need. Customers are looking for the ability to inject a fault and verify that the design hardware or software. They also need end-to-end FuSa solutions where they can do the analysis, generate fault campaigns, and output hardware metrics to see whether the design is ISO 26262 compliant or not. That is the focus in our organization. We are delivering end-to-end FuSa solutions where customers can fully rely on an ISO 26262 certified solution coming from Siemens EDA to validate their chips.

Looking into the future, power, performance and functional safety will continue to grow in importance.

LR: To conclude, you have been working in the hardware-assisted verification domain for quite a while. What are some of the aspects of the job that continue to motivate and fascinate you most?

VC: Siemens is a great company to work for. The Siemens culture, the processes, and the open-door policy are highly motivating for me. Open door means that you can approach anyone, people interact and cooperate with each other as a team. We do not pursue our individual success, rather we aim to achieve our division success, our company success and, by reflection, that makes us successful. We all recognize each other.

As important for me is that at Siemens we are able to drive our roadmaps and not depend on anybody else. I love to talk to customers, learning what they are doing, and where they are going in five years down the road. Understanding the above, feeding it back to the division to build the products around it pleases me greatly.

LR: Thank you, Vijay.

VC: Thank you, Lauro.

Also read:

UVM Polymorphism is Your Friend

Delivering 3D IC Innovations Faster

Digital Twins Simplify System Analysis

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