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Sr Principal Design Engineer

Sr Principal Design Engineer
by Admin on 09-15-2022 at 2:13 pm

  • Full Time
  • Beijing, China
  • Applications have closed

Website Cadence

Specific duties include:

  • Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
  • Proficiency in logic design, simulation, synthesis, STA and testing
  • Proficiency in Verilog and its simulation environment
  • Good knowledge of IC design
  • At least five years’ experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements:

  • Essential Qualifications: Must have BS degree with 8+ years of applicable experience, MS degree with 6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
  • Essential that the individual demonstrates strong communication, verbal and written.
  • Requires good communication skills in English.
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