Graduate Verification Engineer

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team!

This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!

ABOUT SYSTEM IP

This role is for the Interconnect product team.

The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive etc. The highly scalable IP is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performance points.

WHAT WILL I BE ACCOUNTABLE FOR?

You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification.

The responsibilities of a member of the Verification team are:

– Reviewing and assessing proposed design changes from a verification complexity point of view

– Ownership of verification environment from investigation all the way to verification closure

– Investigating and scripting new verification flows and optimising existing ones

– Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug

– There will be opportunities for improving our verification methodology and mentoring other members of the team

– Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system.

Essential skills and experience

– You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment.

– You have experience of using SystemVerilog and UVM

– Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms.

– You are familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process.

– You are competent developing verification flows, making the best use of EDA tools and have good scripting skills

– Strong communication skills and ability to work well as part of a team.

– Dedicated with a focused approach to problem analysis and solving.

– You are able to plan and estimate your own work

Desirable skills

– Team leadership and mentoring experience

– Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)

– Experience in Formal Verification testbenches is a plus.