I am at ARM TechCon today. One interesting presentation was made jointly between Samsung, Cadence and ARM themselves about developing physical libraries (ARM), a tool flow (Cadence) and test chips (Samsung). It was titled Samsung ARM and Cadence collaborate on the silicon-proven world first 14-nm FinFET Cortex-A7 ARM CPU and the presentation was just what it said on the label. This chip was announced late last year but there was a lot more detail today than I have seen before.
Taejoong Song of Samsung kicked off with some details of the Samsung process and of the chip. The design consists of an ARM Cortex-A7 (Bluefin) and 128Mbit SRAM. The reason for all the SRAM is to allow the chip to be used as a process driver. The process has a 78nm gate pitch and a 64nm metal pitch and an 84nm SRAM bitcell. One mystery was that Taejoong mentioned an “innovative diffusion break scheme” which I have no idea what it might be. They reckon that the process is 14% smaller than 20nm planar even though I believe most of the BEOL (metal and vias) is carried over unchanged.
The chip worked. It passed full scan at a Vdd of 660mV for both CPU and memory (which were in separate power domains). So the process has passed basic validation. PDKs and libraries are ready, as is the SRAM compiler and a 1.8V GPIO.
Next up was Rahul Deokar of Cadence. He talked about the changes necessary to the Cadence tool-chain, some of which are due to FinFET and some of which are due to 14nm. First, the Virtuoso flow was updated to be FinFET ready and double patterning correct. Encounter (synthesis, place & route), timing verification, extraction and physical verification were all updated.
There were two big issues that I’d not heard about before. The first was that wire resistance is rising exponentially especially at 20nm and below. This means that a variable thickness metal stack is essential: lower layers have higher resistance and thus lower performance, whereas higher metal layers are lower resistance and faster. As a result, the tool needs to make smart use of the metal, getting critical signals up to the faster upper layers. To make this happen the tool is now multi-threaded and can make simultaneous changes to logic (synthesis), placement and routing. It is also twice as fast as the single-threaded version.
The second problem is pin access. It is a critical design closure metric. With the complex design rules libraries may be impossible to route even if congestion is low. So pin access needs to be taken into account during placement so that cells are spaced out if pin access is too low. A new algorithm plans globally how the router will get to each pin.
These two factors, optimizing use of metal layer assignment and pin access results in an improvement of 57% in operating frequency.
Finally it was Wolfgang Helfricht of ARM’s physical IP division. ARM started in early 2012 to engage with Samsung on bi-directional R&D. During 2013 they produced the physical IP. Early 2014 risk production can be done and late 2014 volume manufacturing.
Obviously ARM’s libaries have to be updated to the FinFET world, with higher resistance and capacitance. The higher drive current of FinFETs also makes IR drop analysis more critical. The libraries also need to be double patterned. The polygons of the IP can be fully colored (assigned to a mask), partially colored or grey (unassigned, left for during physical design).
The portfolio consists of 9-track and 10.5 track standard cell libraries, 7 memory compilers and the GPIO. There are multiple tapeouts and everything is ready now for design starts.
Finally Wolfgang left us with a warning: expect painful learning if you have never done a FinFET or double-patterned design. Allow extra time in the schedule.Share this post via: