New details on Altera network-on-FPGA

Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with programmable logic?

One of our own SemiWiki readers left this comment in a discussion on one of these SoC architectures a while back:

What would be interesting is some NoC tools that can abstract the buses away so that you are not stuck with a particular AMBA/AXI implementation and can use the FPGA fabric for communication transparently without knowing what buses are being used.

The academic community has also been contemplating the benefits for a while. Mohamed Abdelfattah gave an interesting talk in a University of Toronto seminar a couple years ago – his introduction lays out the benefits of NoCs over unstructured FPGA interconnects, and he raises a scenario of an FPGA-tuned hybrid hard/soft NoC and its advantages.

Point of that discussion: don’t just grab NoC IP and take the DIY route to lay it on top of an FPGA design. What is needed is a much more integrated approach, which delivers benefits with efficiency. Last year, Arteris announced that Altera licensed FlexNoC, and a lot of folks were wondering what that would look like. The press release gave some non-specifics about timing margin and frequency requirements, and we’ve been waiting for more to be revealed.

There may have been documentation floating around under NDA, but a few days ago Altera publicly updated the user manuals for the Arria 10 MPSoC as they ramp up from sampling (now) to general availability (soon). I’m not here to debate “industry’s only 20nm”, or the DSP capability, or the competitive timing – we’ll leave that for some other day. I want to focus on the difference the Arteris NoC makes when tightly integrated into an FPGA.

The new document of interest is the Arria 10 Hard Processor System TRM Chapter 7, System Interconnect. A big point of interest is the seven independent level 4 buses, each on its own clock domain. This allows data traffic to flow at multiple performance levels. To our reader comment from earlier, the L4 buses also support multiple protocols: AMBA AXI, AHB and AHB-Lite, APB, and Open Core Protocol (OCP).

Security is also right at the top. Using the firewall capability of the NoC, users can configure access privileges on a per-peripheral and in many cases a per-transaction basis. There are actually two layers of firewall on the SDRAM, one working with the accelerator coherency port of the ARM core, and a second used when cache misses occur. This could be a significant architectural plus in not only secure communications, but safety partitioned designs.

It is fast; one sentence says it all:

The main portion of the system interconnect runs at up to half the MPU main clock frequency (mpu_clk).

That would translate to 600 MHz, combined with an 800 MHz FPGA fabric clock. The NoC is not adding a lot of unwieldy overhead getting in the way of performance. There is also the aspect of NoC software abstraction to consider. It would be extremely difficult, not to mention slow and bloated, to recreate what Altera has done integrating the Arteris FlexNoC in this device.

In closing, I’d emphasize while the view from 50,000ft is similar – a dual ARM Cortex-A9 in an FPGA – the details of the Arria 10 MPSoC are quite different from that other device we talk about a lot. It’s hard to say a feature makes something clearly better or worse in the overall context; it really depends on what an application is trying to do that makes one architecture more suitable than the other. This network-on-FPGA approach may open some new doors, particularly in terms of the firewall capability, that were previously hard to implement.

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