TSMC says 'A16' chipmaking tech to arrive in 2026, setting up showdown with Intel

[Daniel Nenni]

Here is the first article from the symposium:

By Stephen Nellis

SANTA CLARA, California (Reuters) -Taiwan Semiconductor Manufacturing Co said on Wednesday that a new chip manufacturing technology called "A16" will enter production in the second half of 2026, setting up a showdown with longtime rival Intel over who can make the world's fastest chips.

TSMC, the world's biggest contract manufacturer of advanced computing chips and a key supplier to Nvidia and Apple, announced the news at a conference in Santa Clara, California, where TSMC executives said that makers of AI chips will likely be the first adopters of the technology rather than a smartphone maker.

Analysts told Reuters that the technologies announced on Wednesday could call into question Intel's claims in February that it will overtake TSMC in making the world's fastest computing chips with a new technology Intel calls "14A."

Kevin Zhang, TSMC's senior vice president of business development, told reporters that the company has developed its new A16 chipmaking process faster than expected because of demand from AI chip firms, without naming specific customers.

AI chip firms "really want to optimize their designs to get every ounce of performance we have," Zhang said.

Zhang said that TSMC does not believe it needs to use a ASML's new "High NA EUV" lithography tool machines to build the A16 chips. Intel last week revealed that it plans to be the first to use the machines, which can cost $373 million each, to develop its 14A chip.

TSMC also revealed a new technology for suppling power to computer chips from the backside of the chip, which helps speed up AI chips and will be available in 2026.

Intel has announced a similar technology intended to be one of its primary competitive advantages.

Analysts said the announcements called into question Intel's claims that it will retake the world chipmaking crown.

"It's debatable, but on some metrics, I don't think they're ahead," Dan Hutcheson, vice chair at analyst firm TechInsights, said of Intel.

But Kevin Krewell, a principal at TIRIAS Research, cautioned that both Intel and TSMC's technologies remain years away from delivering the technology and will need to prove that real chips match their keynote presentations.

TSMC says 'A16' chipmaking tech to arrive in 2026, setting up showdown with Intel

SANTA CLARA, California (Reuters) -Taiwan Semiconductor Manufacturing Co said on Wednesday that a new chip manufacturing technology called "A16" will enter production in the second half of 2026, setting up a showdown with longtime rival Intel over who can make the world's fastest chips. TSMC...

www.yahoo.com

 

[Daniel Nenni]

Kevin Zhang is wright, it will not require HNA-EUV to do the next generation of "Ax" chips but they will be easier to design and at a much lower cost (10-20%) with HNA-EUV. The advantage Intel has is they only have to make Intel CPU chiplets with HNA-EUV while TSMC has to do full chips, chiplets, and whatever else their customers require. The real question is when will ASML be able to make enough of the HNA-EUV systems to be used for HVM by Samsung, Intel, and TSMC for foundry work?

I was also told by a Dutch friend that TSMC will get the second ASLM machine this year for R&D but HNA-EUV will be too late for A16 HVM for foundries. TSMC would not confirm nor deny which is normal for TSMC. TSMC needs to sell what PDKs are available today versus what might be available in the future.

Dan Hutchinson is correct, if you only look at Intel IDM designed chiplets using BSPD and HNA-EUV they are ahead. If you look at the foundry business Intel is behind TSMC by a wide margin. Based on what I know personally and what was said at the Symposium, TSMC N2 will have more design wins than TSMC N3 which was an impressive number! So who exactly is using Intel 18A and Samsung N2?

Kevin Krewell is wrong and hopefully misquoted. TSMC errs on the side of caution, others do not.

 

[Mooredaddy]

Kevin Zhang is wright, it will not require HNA-EUV to do the next generation of "Ax" chips but they will be easier to design and at a much lower cost (10-20%) with HNA-EUV. The advantage Intel has is they only have to make Intel CPU chiplets with HNA-EUV while TSMC has to do full chips, chiplets, and whatever else their customers require. The real question is when will ASML be able to make enough of the HNA-EUV systems to be used for HVM by Samsung, Intel, and TSMC for foundry work?

I was also told that by a Dutch friend that TSMC will get the second ASLM machine this year for R&D but HNA-EUV will be too late for A16 HVM for a foundries. TSMC would not confirm nor deny which is normal for TSMC. TSMC needs to sell what PDKs are available today versus what might be available in the future.

Dan Hutchinson is correct, if you only look at Intel IDM designed chiplets using BSPD and HNA-EUV they are ahead. If you look at the foundry business Intel is behind TSMC by a wide margin. Based on what I know personally and what was said at the Symposium, TSMC N2 will have more design wins than TSMC N3 which was an impressive number! So who exactly is using Intel 18A and Samsung N2?

Kevin Krewell is wrong and hopefully misquoted. TSMC errs on the side of caution, others do not.

Hey Dan, what did you hear about N2?

 

[Daniel Nenni]

Hey Dan, what did you hear about N2?

I heard everything, and then some! What do you want to know?

 

[NY_Sam2]

Dan, any number like BEOL M0 pitch, CPP, Cell Height for N2? EUV masks number reduction from N3 to N3E?

 

[Mooredaddy]

I heard everything, and then some! What do you want to know?

View attachment 1866

Dan’s the man!! How’s first gen GAA yielding on N2? PDK coming along nicely? Density still as anemic as first reported?

 

[NY_Sam2]

A16 = GAA + Backside Power, source = Tom's Hardware

 

[Daniel Nenni]

Hey Dan, what did you hear about N2?

I heard more about N2 from the ecosystem than the symposium but TSMC did show that the N2 D0 was the same as N3 based on the ramp timeline. They also said N2 would be production ready in 2H 2025. The ecosystem is doing N2 test chips and we may see some N2 tape-outs this year if PDK 1.0 makes it in time which I believe it will. Will Apple have N2 product shipping in 2025? Yes, I believe they will.

The bad news is that Intel 18A is not doing as well so N2 and 18A will be a close finish for foundry customers. Notice I said foundry customers and not Intel inside designs. N2 of course will have better paper specs than 18A but I need to see some tape-outs (not tape-ins) to better judge this. Unfortunately finding 18A tape-outs (not tape-ins) is proving hard to do thus far.

I can tell you though that all of the early N3 customers are doing N2 and even TSMC said N2 will have more tape-outs than N3 at this time in the ramp. That is VERY big news! I had thought some people would skip N2 in favor of 16A but that is definitely not the case.

The N2 performance and density numbers were actually better than what I heard last year but TSMC really wanted to talk about 16A and SPR:

 

[Daniel Nenni]

Dan, any number like BEOL M0 pitch, CPP, Cell Height for N2? EUV masks number reduction from N3 to N3E?

Nope, not publicly. Scott Jones probably has those numbers but you would need to buy a report from TechInsights now that they bought his company.

 

[Mooredaddy]

I heard more about N2 from the ecosystem than the symposium but TSMC did show that the N2 D0 was the same as N3 based on the ramp timeline. They also said N2 would be production ready in 2H 2025. The ecosystem is doing N2 test chips and we may see some N2 tape-outs this year if PDK 1.0 makes it in time which I believe it will. Will Apple have N2 product shipping in 2025? Yes, I believe they will.

The bad news is that Intel 18A is not doing as well so N2 and 18A will be a close finish for foundry customers. Notice I said foundry customers and not Intel inside designs. N2 of course will have better paper specs than 18A but I need to see some tape-outs (not tape-ins) to better judge this. Unfortunately finding 18A tape-outs (not tape-ins) is proving hard to do thus far.

I can tell you though that all of the early N3 customers are doing N2 and even TSMC said N2 will have more tape-outs than N3 at this time in the ramp. That is VERY big news! I had thought some people would skip N2 in favor of 16A but that is definitely not the case.

The N2 performance and density numbers were actually better than what I heard last year but TSMC really wanted to talk about 16A and SPR:

View attachment 1870

I guess the read through for this is that N2 derived processes must be promising (i.e N2P, N2X) to make N2 jump worth it. SPR is what TSMC is calling BPD right? Also N2P and N2X are using BPD right?

 

[Daniel Nenni]

I guess the read through for this is that N2 derived processes must be promising (i.e N2P, N2X) to make N2 jump worth it. SPR is what TSMC is calling BPD right? Also N2P and N2X are using BPD right?

Yes and no. No SPR on N2. It first arrives on A16.

 

[Xebec]

Kevin Zhang is wright, it will not require HNA-EUV to do the next generation of "Ax" chips but they will be easier to design and at a much lower cost (10-20%) with HNA-EUV. The advantage Intel has is they only have to make Intel CPU chiplets with HNA-EUV while TSMC has to do full chips, chiplets, and whatever else their customers require. The real question is when will ASML be able to make enough of the HNA-EUV systems to be used for HVM by Samsung, Intel, and TSMC for foundry work?

I’m trying to unpack this a little — Has Intel stated that their 14A process is only for Intel CPU chiplets and nothing else? Or is it more in the 2026-2027 timeframe that we’re talking? (Or will “non Intel CPU chiplets” run 14A without High NA processing?) I thought Intel 14A was meant to be a full foundry offering.

EDIT: I get why TSMC is using A before the number for their processes, but now it’s confusing me with Apple A-series chips that often drive TSMC process

 

[IanD]

Do note the small print for A16-SPR though -- the power/speed/area improvements are for "Datacenter AI products", or from the slide "Best suited for HPC products with complex signal routes and dense power delivery networks".

In other words, big chips with relatively high clock rates/supply voltages and high power/current densities, where the voltage drops in the (big heavy) on-chip power grid are significant (and chip power is high) -- so AI accelerators and GPUs and terabit router/switch chips, and possibly massively-parallel CPUs. In other words the sexy "hot chips" -- literally... ;-)

For devices which don't fall into this category -- which probably means the majority of SoC/ASIC designs -- the advantage will be rather smaller, and there is a significant wafer cost penalty (which was carefully not mentioned), and N2/N2P is likely to be more appropriate.

At least, that's what TSMC told us... ;-)

 

[Xebec]

N3 to N2 was a “>1.15x” Density increase, and N2 to A16 is ~ 8.5%. Intel 14A is slated for a 20% density increase over 18A.

These numbers seem a little anemic..

 

[IanD]

N3 to N2 was a “>1.15x” Density increase, and N2 to A16 is ~ 8.5%. Intel 14A is slated for a 20% density increase over 18A.

These numbers seem a little anemic..

That's because there's very little change in the metal pitches from N3 to N2 or A16 (renamed N2 with BSPD).

N3==>N2 is similar to 20nm==>16FF (different transistors, similar metal stack), N2==>A16 is just going from front-side to back-side power.

In both cases there's a significant performance/power increase but only a small density improvement. Note that there's also a significant NRE and wafer cost increase in both cases which IIRC is bigger than the density improvement... :-(

 

[Daniel Nenni]

Do note the small print for A16-SPR though -- the power/speed/area improvements are for "Datacenter AI products", or from the slide "Best suited for HPC products with complex signal routes and dense power delivery networks".

In other words, big chips with relatively high clock rates/supply voltages and high power/current densities, where the voltage drops in the (big heavy) on-chip power grid are significant (and chip power is high) -- so AI accelerators and GPUs and terabit router/switch chips, and possibly massively-parallel CPUs. In other words the sexy "hot chips" -- literally... ;-)

For devices which don't fall into this category -- which probably means the majority of SoC/ASIC designs -- the advantage will be rather smaller, and there is a significant wafer cost penalty (which was carefully not mentioned), and N2/N2P is likely to be more appropriate.

At least, that's what TSMC told us... ;-)

Wouldn't that be the same for Intel BSPD? Or is this TSMC specific? Also the TSMC and Intel implementations are different. Do you have thoughts on why TSMC did that?

 

[IanD]

Do note the small print for A16-SPR though -- the power/speed/area improvements are for "Datacenter AI products", or from the slide "Best suited for HPC products with complex signal routes and dense power delivery networks".

In other words, big chips with relatively high clock rates/supply voltages and high power/current densities, where the voltage drops in the (big heavy) on-chip power grid are significant (and chip power is high) -- so AI accelerators and GPUs and terabit router/switch chips, and possibly massively-parallel CPUs. In other words the sexy "hot chips" -- literally... ;-)

For devices which don't fall into this category -- which probably means the majority of SoC/ASIC designs -- the advantage will be rather smaller, and there is a significant wafer cost penalty (which was carefully not mentioned), and N2/N2P is likely to be more appropriate.

At least, that's what TSMC told us... ;-)

For example, the "TSMC headline figures" for A16(SPR) vs N2P are +8%-10% speed, -15%-20% power, +10%-15% logic density, +5%-8% chip density.

But this is for high-current fast-clocking chips with a high PWR/GND grid density (20%-30%), which is what they benchmark with -- a lot of the savings come from reduced track length by getting rid of the topside power grid.

If you drop that grid density down to 10% or less (slower low/medium power chips where efficiency is the key) then the improvements drop to <5% in speed, <10% power, <5% logic density, <3% chip density -- which is why TSMC advise that A16-SPR is "Best suited for HPC products with complex signal routes and dense power delivery networks". And don't ask about the cost adder... :-(

The other hidden gotcha is that all this heat (can be >1kW nowadays...) has to get out through all the topside metal/oxide layers (instead of backside through the bulk) which have higher thermal resistance, so the transistors (and metal) run considerably hotter compared to the heatsink. Which is OK if you're liquid cooling (HPC again...) and can provide a nice cold cooling plate, but not so good with air cooling in many applications where the heatsink runs a lot hotter.

So for the right application (e.g. high-priced liquid-cooled AI/HPC -- which will be *massive*) A16-SPR is a great process, but this isn't true for a lot of applications where N2P is a better choice -- and of course TSMC offer both, unlike Intel. Horses for courses... ;-)

 

[IanD]

Wouldn't that be the same for Intel BSPD? Or is this TSMC specific? Also the TSMC and Intel implementations are different. Do you have thoughts on why TSMC did that?

Same for Intel, the reasons are the same even though the exact implementation is different -- but of course all Intel's products are high-speed high-current, unlike TSMC (who also have N2P for the others). Maybe Intel took more risk (more radical BSP structure) and TSMC decided to play it safer? I think we all know what happened last time Intel tried to make too big a technology jump too fast... ;-)

 

[nghanayem]

A16 = GAA + Backside Power, source = Tom's Hardware

View attachment 1869

N3 to N2 was a “>1.15x” Density increase, and N2 to A16 is ~ 8.5%.

I obviously can’t say for sure, but it seems like TSMC is relaxing interconnect pitch for A16. By going to BS contacts they don’t need M2 or M0 power rails. Just looking at TSMC’s tried and tested 6T HD cell, removing the two power rails should reduce cell height by 1/3. And unlike the intel 4 + powervia material TSMC shouldn’t need keep out zones that blunt some of the improvements. The only logical explanations I can think of for why A16 density bump is what it is are TSMC increasing sheet width for all devices for better drive/performance, and or relaxing metal pitches for cost/performance/lowering energy losses.

Intel 14A is slated for a 20% density increase over 18A.

When did intel say that?

 

[IanD]

I obviously can’t say for sure, but it seems like TSMC is relaxing interconnect pitch for A16. By going to BS contacts they don’t need M2 or M0 power rails. Just looking at TSMC’s tried and tested 6T HD cell, removing the two power rails should reduce cell height by 1/3. And unlike the intel 4 + powervia material TSMC shouldn’t need keep out zones that blunt some of the improvements. The only logical explanations I can think of for why A16 density bump is what it is are TSMC increasing sheet width for all devices for better drive/performance, and or relaxing metal pitches for cost/performance/lowering energy losses.

When did intel say that?

I doubt that anyone will disclose exact pitches and changes to cell structure/layout with N2 because of NDA, but there are various detail changes -- some not obvious -- to increase density and improve access resistance both with N2 and N2-SPR. The metal stack is similar to N3, no big changes, but as usual there are high-density and high-performance cells which trade off density for capacitance/speed.