TSMC says 'A16' chipmaking tech to arrive in 2026, setting up showdown with Intel
- Thread starter Daniel Nenni
- Start date
Yes. Most of the PPA improvement we saw from N5/N4 to N3 were due to the mixed-height FlexFin libraries -- the high-density M143 library is actually alternating rows of 1-fin H117 (for low-power non-critical paths) and 2-fin H169 (for critical paths), and there are also tall H286 cells (one row of each) used for complex cells like latches, especially multibit ones. If you benchmark just the two-fin libraries as a direct process comparison then the improvement from N5/N4 to N3 is considerably reduced. There's also a 3-fin HPC library in N3 (and I assume a mixed height library using this?) but we didn't use that because we care about power/efficiency more than flat-out speed.
I don't have details of the N2 libraries yet but I expect the overall structure to be similar -- though it's also possible TSMC could make use of the ability to vary transistor width with nanosheet (impossible with FinFET) this could make library gridding an absolute nightmare, so I don't know if this will be done or not.
SPIE Conference ~ Feb 28, 2024
Traced it back to the source, many sites are interpreting the last line as 20% density, but that may be wrong:
Anne Kelleher, senior vice president of Intel, who was a speaker, said, “Chips made with 14A have more than 15% higher performance per watt than the 1.8 nanometer (18A) process,” adding, “In the case of the ‘14A-E’ process, which increases performance by 5% from 14A, “Chip integration will be improved by 1.2 times compared to 18A,
[단독] 삼성보다 한박자 빠른 인텔…이번엔 '1.4나노' 도발
파운드리(반도체 위탁 생산) 부활을 선언한 미국 인텔이 잇달아 1나노(나노미터·10억분의 1m)급 공정에서 기술력을 과시...
m.sedaily.com
EDIT: Also seeing it here, with an earlier date than the above article, from someone referring to the SPIE conference: https://lithoguru.com/life/?p=711
“ But interestingly, the 14A node is expected to have a transistor density that is only 1.2X the 18A node”
Maybe lithogru had a mix up between i3 and 18A, because 14A is most definitely not part of 5N4Y and intel has said that 14A is when intel plans to go back to a relaxed 2 year cadence.SPIE Conference ~ Feb 28, 2024
Traced it back to the source, many sites are interpreting the last line as 20% density, but that may be wrong:
Anne Kelleher, senior vice president of Intel, who was a speaker, said, “Chips made with 14A have more than 15% higher performance per watt than the 1.8 nanometer (18A) process,” adding, “In the case of the ‘14A-E’ process, which increases performance by 5% from 14A, “Chip integration will be improved by 1.2 times compared to 18A,
[단독] 삼성보다 한박자 빠른 인텔…이번엔 '1.4나노' 도발
파운드리(반도체 위탁 생산) 부활을 선언한 미국 인텔이 잇달아 1나노(나노미터·10억분의 1m)급 공정에서 기술력을 과시...
EDIT: Also seeing it here, with an earlier date than the above article, from someone referring to the SPIE conference: https://lithoguru.com/life/?p=711
“ But interestingly, the 14A node is expected to have a transistor density that is only 1.2X the 18A node”
Fair — though 20% density increase over 2-3 years already seems fairly relaxed? I guess we’re entering the era where a 10% density increase counts as a major node..
That's because pitches are shrinking much more slowly nowadays than suggested by the node names, the area/power improvements are now largely coming from DTCO (things like COAG/PODE/FlexFin/NanoFlex --and special design rules only allowed in carefully-controlled "digital" areas"...) and not so much raw process improvement. For example, actual physical gate length has been around 16nm-17nm for several nodes now, regardless of the node label (N7/N6/N5/N4/N3)...
hist78
Well-known member
The 2H2026 target for TSMC A16 production is critical because Intel's 14A with Hi-NA
will be coming out more or less the same time.
That means for all those who want to be on the leading edge nodes, they must make the decision now, if they haven't done so. My thought is unless the fabless companies have extra money (huge amount of money) and extra engineering resources, they probably will only choose one and a safe one.
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Remember, Intel design will have access to 14A much sooner than Intel Foundry customers. I'm still trying to figure out how many NA systems will be required for Intel to be in HVM with 14A. It will be even more challenging for TSMC since they will need many more HNA EUV systems for HVM.
Optional.
hist78
Well-known member
It's a very different risk management attitude between Intel and TSMC. Intel believes in two years ASML, various ASML partners and Intel itself will sort out all the issues related to Hi-NA tools while TSMC plans to go live in A16 without using Hi-NA.
Do you think Intel is too optimistic or TSMC is too conservative?
I think Intel is being an IDM and TSMC is being a foundry. Intel can do chiplets but TSMC must do full chips right out of the gate (Apple, MediaTek, qcom, etc...). I like the competition and have no problem explaining the differences to people. I get the most interesting calls from Wall Street.
hist78
Well-known member
If I understand what you have said, Intel can successfully adopt Hi-NA tools by 2026/2027 under strictly Intel defined criteria?
But Intel can only control what they can control, not much for those issues inside ASML or ASML's suppliers.
IMO, ASML did not always deliver the roadmap tool on schedule. Refer to the graph from ASML 2023 annual report, ASML wants to reduce cost and development time in parallel by co-working with imec. To expedite learning curve for HVM in 2026, high volume Hi NA EUV wafers needed for learning, but imec does not have that volume. There is a magic number (100K) of wafers in the past for technology to be matured. Will intel produce >100k 14A wafers in 2026 for learning? It will be quite interesting and expected to see IFS-ASML announce joint-project of Hi NA EUV HVM by 2026.
hist78
Well-known member
According to this graph, there isn't much time left (1.5 to 2 years) before starting Hi-NA EUV HVM.
If ASML can't meet that target, can Intel scale back to the low NA EUV tools for Intel 14A?
The original ASML EUV systems were delayed by YEARS. I remember going to SPIE and we laughed when ASML did roadmaps. Hopefully they have figured out HNA-EUV but I'm betting they cringe when Pat Gelsinger speaks about it.
Since Intel does not have to do full chips or high volumes they may get away with it. TSMC however cannot bet the whole company on a new technology. Look at what they did with EUV. Bolted it on 7nm and eased it in to 6nm. The rest of course is history.
Has ASML said how many HNA systems they will ship over the next five years? Is it enough for Intel, Samsung, and TSMC to all be in HVM?
So I have two questions: When will HNA-EUV be production ready? When will ASML ship the systems required for Intel, Samsung, and TSMC to do HVM?
hist78
Well-known member
The original ASML EUV systems were delayed by YEARS. I remember going to SPIE and we laughed when ASML did roadmaps. Hopefully they have figured out HNA-EUV but I'm betting they cringe when Pat Gelsinger speaks about it.
Since Intel does not have to do full chips or high volumes they may get away with it. TSMC however cannot bet the whole company on a new technology. Look at what they did with EUV. Bolted it on 7nm and eased it in to 6nm. The rest of course is history.
Has ASML said how many HNA systems they will ship over the next five years? Is it enough for Intel, Samsung, and TSMC to all be in HVM?
So I have two questions: When will HNA-EUV be production ready? When will ASML ship the systems required for Intel, Samsung, and TSMC to do HVM?
"So I have two questions: When will HNA-EUV be production ready? When will ASML ship the systems required for Intel, Samsung, and TSMC to do HVM?"
This is a billion dollar question.
ASML annual report told us HNA EUV scanner HVM will be introduced and validated from 2026. It is from vendor's point of view. What will be the results from intel, tsmc and Samsung? It is planned in intel 14A, not in tsmc A16 and no update in SF for 2026.