Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. In this webinar, the focus will be on the functional verification of the RTL with the power intent defined …
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Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We keep developing new performance optimizations that are delivered with each new release of Xcelium. It is easy to achieve …
Date: Tuesday, December 13, 2022 Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We …
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus …
Continue reading "CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation"
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles. Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles to achieve the desired target coverage and …
Continue reading "Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster"
Crack the Verification Double Trouble! Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles. Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles to achieve …
Continue reading "CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML"
Date: Wednesday, June 7, 2023 Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM) foundation, Xcelium automates …
Continue reading "Webinar: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance"
Date: Wednesday, June 7, 2023 Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM) foundation, Xcelium automates …
Continue reading "CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance"
In-Person Seminar - June 12, 2023 Shefayim Convention Center, Israel Summary: As verification tasks become increasingly more challenging and complex, we need to look for advanced techniques and solutions to improve and shorten the verification cycle to boost productivity. Cadence® is pleased to bring you a full-day seminar covering all aspects of the verification flow. …
Date and time: Thursday, September 7, 13:00-14:15 Organizer: Cadence Design Systems Japan Innotech Co., Ltd. IC Solution Division Cost: Free Venue: Online (Zoom webinar) *It is also possible to participate from a web browser. We recommend using Google Chrome, Firefox, or Chromium Edge. Registration deadline: Wednesday, September 6, 16:00 The introduction of low-power methods such …
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before. What You'll Gain: Insight: Understand why the Xcelium MC App is crucial for DV engineers looking …
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Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps, including technical complexity, lack of resources, and shifting requirements. In constrained random environments, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity, persistence, and technical expertise. A …
Continue reading "Webinar: Verisium SimAI: Coverage Gaps Meet Their Match"
Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps, including technical complexity, lack of resources, and shifting requirements. In constrained random environments, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity, persistence, and technical expertise. A …
Continue reading "Verisium SimAI: Coverage Gaps Meet Their Match"
