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Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster

February 8

Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.

Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles to achieve the desired target coverage and finding as many bugs as possible using less time and resources. However, with stringent tapeout schedules, you are expected to do this quickly, with no compromise to verification efficiency and regression throughput. All of us are resource constrained, so if you can hit the most likely “difficult” scenarios faster, you are saving real engineering time.

This webinar will cover topics including:

  • How Xcelium simulator with the Machine Learning (ML) App is dramatically more efficient than regular regression in stress testing of corner cases
  • How Xcelium ML App customizes both functional coverage and code coverage
  • Using the Xcelium ML App for regression flow to improve the efficiency of your regression environment, save CPU cycles, improve bug-hunting efficiency, and speed up coverage closure

REGISTER HERE

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