Synopsys Northern Europe is hosting a Technical Symposium providing updates on all aspects of doing state of the art designs at emerging and established nodes. This event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that our experts will …
Customers love the Synopsys Analog Design Solution and have been adopting it at a record pace. Now it's available on the cloud. Synopsys Cloud Analog Instance includes everything you need to get started quickly: software, hardware setup, training, and scripts to help setup and manage your design. Designers not only have access to a full …
Synopsys Webinar | Thursday, November 9, 2022 | 10 a.m. Pacific REGISTER HERE Functional ECOs (engineering change orders) are an important part of the design cycle, enabling design teams to respond quickly to frequent, unexpected, and last-minute register-transfer logic (RTL) functional changes. ECOs are unavoidable, however, they are necessary to fix functional verification bugs or …
Wednesday, November 16, 2022 | 9:00 am - 2:00 pm ET | 3:00 pm - 8:00 pm CET Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not …
Nov 29th, 2022 | 8:00 AM PST Nov 30th, 2022 | 8:00 AM GMT+8 Join this Virtual Event Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges are exacerbated, while the latest technology nodes …
Synopsys Webinar: Wednesday, November 30, 2022 | 10:00 - 11:00 a.m. Pacific Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers with its output at any given time depending …
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Historically, the digital design process requires in-depth knowledge of each tool in the cycle. Getting up and running involves writing hundreds of lines of script. Many companies lack the resources or in-house expertise. This is where a cloud-based, expert-built digital design flow can deliver a big productivity lift. By designing with a prescribed, tailored flow …
Summary For over a decade, CPU and GPU design companies have been using Synopsys VC Formal Datapath Validation (DPV) app with its HECTOR™ technology to verify their data processing elements because traditional verification methods cannot exhaustively verify the correctness of mathematical computations in these designs. Like CPUs and GPUs, AI processors are also datapath heavy …
Join our FREE online event to learn about the latest features and performance enhancements in the QuantumATK U-2022.12 product release. See how QuantumATK can provide impactful ROI on: Quality of …
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*Company email required for registration* If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In addition to power, latency is another key concern …
Continue reading "Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs"
Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how …
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What is SIPI SIG? This event provides the opportunity for networking and proactive discussion with SIPI engineers to increase awareness of signal and power integrity issues within a forum for engaging dialog and education. Synopsys SIPI SIG is for Synopsys customers, and partners to update the audience about their offerings as well as for Synopsys …
*Company email required for registration* Register Transfer Level (RTL) power analysis, performed early in the design cycle, is a key component of end-to-end methodology to maximize energy efficiency. Such analysis has become a critical requirement for many IC designs today and in the future. Although RTL power analysis technology has been available to designers for …
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