Webinar: PCIe/CXL Latency and Power Considerations for HPC SoCs

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If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In addition to power, latency is another key concern for HPC and data center SoC designers as access to the available memory pool is becoming a bottleneck and must be allowed in nanoseconds.

Attend this webinar to learn more about some of the power reduction mechanisms, such as L0p power state, clock power gating, and static and dynamic voltage scaling, as well as datapath latency reduction techniques in the PCIe 6.0 and CXL 2.0/3.0 specifications.

Learn how to use tailored IP to make latency and power tradeoffs to achieve the optimal results for your HPC and data center SoCs.

SPEAKERS: Madhumita Sanyal, Sr. Technical Manager and Gary Ruggles, Sr. Product Manager

Madhumita Sanyal is a Senior Technical Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 17 years of experience in design and application of ASIC WLAN products, logic libraries, embedded memories, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business. 

Gary Ruggles is the Sr. Product Manager for PCIe, CXL, CCIX, and SATA Controllers.  Gary has over 25 years of experience in the semiconductor industry, and has spent the last 20 years in sales, marketing, and business development roles for multiple semiconductor IP companies, including PLDA, Kool Chip (now Invecas), Snowbush IP (now Rambus), ARM/Artisan and Cadence (Tality), focusing on PHYs and PCIe controller IP.

*This webinar is in partnership with SemiWiki and Synopsys*

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