In this upcoming webinar, learn how chains and constellation objects model groups of satellites or other space objects that operate together. You’ll understand how the constellation object represents a group of satellites or space vehicles that follow specific orbits and configurations. TIME: MARCH 13, 2024 11 AM EDT / 4 PM CET / 8:30 PM …
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to …
Continue reading "Webinar: Efficient Design Methodology for 112G Interface Compliance"
Join us for Part 2 of the Multibody Cislunar Design: A Tour of Concepts webinar, where we’ll review dynamical systems concepts, including fixed point solutions (i.e., libration/Lagrange points) and periodic orbits. TIME: MARCH 21, 2024 11 AM EDT / 4 PM CET / 8:30 PM IST Venue: Virtual Overview During Part 2 of The Multibody Cislunar …
Continue reading "Webinar: Multibody Cislunar Design: A Tour of Concepts (Part 2)"
Design, Automation and Test in Europe Conference | The European Event for Electronic System Design & Test DATE 2024 - Call for Papers The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in the hardware and software design, test and manufacturing of …
ISQED'24 Conference Information The 25th International Symposium on Quality Electronic Design (ISQED'24) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology, packaging, assembly & test to achieve total design quality. Past ISQED events have been held with the technical sponsorship of IEEE …
In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and …
The 2024 NAFEMS Eastern Europe Conference will be held on the 24th and 25th of April, 2024 in Kraków, Poland. This event is where the regional simulation engineering community comes together to discuss …
Managing the thermal aspects of electronics to avoid excessive heat buildup has a direct impact on reliability. By conducting thorough thermal analysis early in the design processes, engineers can identify …
Continue reading "Webinar: Thermal Solutions for Electronics Design"
DATE: Wednesday, April 24 TIME: 8:00am PDT | 11:00am EDT | 4:00pm BST | 8:30pm IST PSpice is a high-performance, industry-proven, mixed-signal simulator and waveform viewer for analog and mixed-signal circuits. As one of the most widely used mixed-mode circuit simulators with extensively available models from component and IC vendors, PSpice simulation technology is applicable for product design in …
Continue reading "Webinar: Design, Simulate, and Validate Your Circuit with PSpice"
Utilizing AWS cloud resources to accelerate variation-aware verification AI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3, 4, 5, 6 and higher sigma targets, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before, many teams are considering running design and verification workloads, including Solido Design Environment, on …
Continue reading "Masterclass: Deploying Solido Design Environment AI Workflows on AWS"
(Work email required for verified registration) During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate across multiple time zones. Often, integrators must integrate design blocks …
Continue reading "Webinar: Automating the Integration Workflow with IP Centric Design"
Date: Tuesday, May 14, 2024 Venue: Hilton Dresden Location: An der Frauenkirche 5, 01067 Dresden, Germany Parking: There is parking at the hotel with a charge of €28 per day. You will receive further information in your registration confirmation email. Analog, RF, and Mixed-Signal IC Design Learn how the latest developments within Virtuoso Studio and Spectre platforms can significantly …
Continue reading "CadenceCONNECT: Tech Days Europe 2024 – Dresden"
REDUCE THE RISK AND COST OF LATE DESIGN, MANUFACTURING CHANGES How to Shorten Development Time and Reduce Costs for Your Next Product If your team utilizes Altair® InspireTM, SimSolid®, and SimLab® in the early stages of product development to improve product performance, or manufacturing simulation like Altair® InspireTM Cast, Altair® InspireTM Form to bring your concepts to …
IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology. …
