Chiplet Summit
San Jose, CAThe First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, …
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WEBINAR: Introduction to UCIe™
OnlineTuesday, February 21, 2023 8:00 am PT / 11:00 am ET UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, …
Webinar: Power Integrity Challenges and Solutions for Interposer Design
OnlineJoin us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated …
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Menta and CEA: Smarter Systems Through Heterogeneous Integration
Dresden, Germany Dresden, GermanyCEA-List and Menta SAS will present together the MOSAICS-LP project, a scalable chiplet platform REGISTER HERE
Webinar: UCIe: On-Package Chiplet Innovation Opportunities
OnlineSynopsys Webinar | Tuesday, August 15, 2023 | 10:00 -11:00 a.m. PDT High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands …
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Webinar: IP Lifecycle Management for Chiplet-Based SoCs
OnlineChiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of …
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Webinar: UCIe-Based Chiplet Verification – from IP to SoC
OnlineDate: Wednesday, August 30, 2023 Time: 11:00am PDT | 1:00pm CDT | 2:00pm EDT Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix …
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Webinar: UCIe-Based Chiplet Verification – from IP to SoC
OnlineAbout Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect …
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CadenceCONNECT: The Race Is On!
Cadence Headquarters, San Jose, CA 2655 Seely Ave, San Jose, CA, United StatesEvent Overview Date: Monday, November 13, 2023 Time: 10:00am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that …
Chiplet Summit 2024
Santa Clara Convention Center 5001 Great America Pkwy, Santa Clara, CA, United StatesAbout the Event The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their …
Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management
OnlineIn a world where the chiplet market is projected to soar to $50.5 billion in revenue by 2024, staying ahead of the game is crucial. This monumental shift in the …
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Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges
OnlineThursday, February 8, 2024 | 9-10 a.m. PT The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There …
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