WEBINAR: Introduction to UCIe™

Online

Tuesday, February 21, 2023 8:00 am PT / 11:00 am ET UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet …

Webinar: Power Integrity Challenges and Solutions for Interposer Design

Online

Join us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation. …

Webinar: UCIe: On-Package Chiplet Innovation Opportunities

Online

Synopsys Webinar | Tuesday, August 15, 2023 | 10:00 -11:00 a.m. PDT High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of today’s data centers, autonomous vehicles, etc. On-package interconnects are a critical component to deliver the power-efficient performance for this evolving landscape. Universal Chiplet Interconnect …

Webinar: IP Lifecycle Management for Chiplet-Based SoCs

Online

Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP …

Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Online

Date: Wednesday, August 30, 2023 Time: 11:00am PDT | 1:00pm CDT | 2:00pm EDT Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets …

Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Online

About Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. …

CadenceCONNECT: The Race Is On!

Cadence Headquarters, San Jose, CA 2655 Seely Ave, San Jose, CA, United States

Event Overview Date: Monday, November 13, 2023 Time: 10:00am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. …

Chiplet Summit 2024

Santa Clara Convention Center 5001 Great America Pkwy, Santa Clara, CA, United States

About the Event The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions …

Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management

Online

In a world where the chiplet market is projected to soar to $50.5 billion in revenue by 2024, staying ahead of the game is crucial. This monumental shift in the IC design ecosystem necessitates a forward-thinking approach to navigate the sea of data and intricate Intellectual Properties (IPs) securely. That's why Keysight has expanded its …

Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges

Online

Thursday, February 8, 2024 | 9-10 a.m. PT The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power …

ESDA Webinar: Chiplet Security – Current and Future

Online

Many semiconductor-based systems are moving toward 2.5D designs consisting of different pre-manufactured chips (chiplets) that perform specific functions. These are often provided by multiple vendors and are typically interconnected using an interposer. However, unlike monolithic multi-function chips, chiplets can be developed anywhere and at any process node. As such, chiplets from untrusted vendors can be …

Webinar: Exploring the Advancement of Chiplet Technology and the Ecosystem

Online

Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the …