Summary The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static …
Continue reading "Webinar: Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs"
Abstract The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification …
Continue reading "Webinar: The Power of Verilog’s PLI and VPI for FPGA Designs"
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach …
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach …
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the …
LIVE WEBINAR: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US) Philipp Wagner, cocotb and Hardware/Software Engineer at lowRISC Thursday, November 9, 2023 11:00 AM - 12:00 PM (PST) Abstract: cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. …
Continue reading "Webinar: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US)"
LIVE WEBINAR: System Simulation of Versal ACAP Designs (US) Louie De Luna, Director of Marketing, Aldec Thursday, November 16, 2023 11:00 AM - 12:00 PM (PST) Abstract: AVersal ACAP, developed by …
Continue reading "Webinar: System Simulation of Versal ACAP Designs (US)"
