LIVE WEBINAR: Enhancing the Simulation Testbench for VHDL-based FPGA Designs (Three Part Webinar Series) Part 1: Basic Testbench for a Simple DUT (US)

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces.

In part 1 of this webinar series, we will show you how to verify a relatively simple DUT with low- to mid-quality requirements using a basic testbench without using any verification framework. We will also discuss the elements of a basic testbench infrastructure, show you examples of how to create self-checking testbenches with verbosity and alert control, and introduce the use of basic Bus Functional Models (BFMs) to speed up verification and debugging.

Having shown you these basic testbench techniques, we will then introduce an open-source industry verification framework for VHDL designs called UVVM that you can use to verify a simple DUT.

Agenda:

• State of the FPGA community for verification
• Achieving readability, maintainability and extensibility
• The elements of a basic testbench infrastructure
• Verbosity control and alert control
• Main testbench architectures
• Basic BFMs
• Getting started with UVVM
• UVVM for basic verification
• Q&A

Webinar Duration

• 45 min presentation/live demo
• 15 min Q&A