GSA: At the Helm Panel Discussion

Have you heard the news? We're hosting an exciting panel discussion on July 8 and are extending a complimentary invite for you to join our webinar, At the Helm. The semiconductor industry is entering an era of tremendous growth in multiple end-markets. Join industry leaders and entrepreneurs as they discuss the opportunities and challenges that companies face, as well …

How to Use Calibre for Physical Verification

Register For This Web Seminar Online - Jul 8, 2020 10:00 - 11:00 Asia/Singapore Register Overview Physical Verification Overview Calibre Physical Verification General Introduction Basic Calibre Process Flow Calibre Hierarchical Processing How to Run Calibre DRC DRC Extension: eqDRC, Fast XOR and Antenna Checks Circuit Verification Process Flow How to Run Calibre LVS LVS Extension: …

ITF USA 2020 LEAP INTO THE SEMICONDUCTOR FUTURE

ITF USA 2020 presents the latest research advances and exciting opportunities in next-generation semiconductor and system scaling. Our virtual event features talks & presentations by imec’s semiconductor experts, as well as a showcase of selected tech solutions. ITF USA also facilitates live & direct interactions with our speakers through Q&A roundtables, and with imec experts …

RISC-V Day Vietnam 2020

Here is the news for RISC-V Day Vietnam 2020 in Ho Chi Minh City on July 14, 2020. The program is going to be online feed. We will have more updates. Tentative Program Schedule (subject to change) Title Speaker(s) RISC-V Efforts at the University of Electro-Communications Cong-Kha PhamThe University of Electro-Communications Title TBD TBD

From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology

Register For This Web Seminar Online - Jul 14, 2020 10:00 AM - 11:00 AM US/Pacific Register Overview Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple manual coding stages, several designers …

Pitfalls of IP Power Estimation for AI & Vision SoCs, and How to Avoid Them

Accurately estimating power for your vision SoC can make the difference between success and a multi-million dollar failure. Estimating power can be fairly straightforward for a RISC processor, but today’s vision SoC designs include neural networks with intense computation requirements making accurate power estimation much complicated. How can a designer have confidence in the power …

Shorten Development Time of Edge AI Solutions

The continuous battle when designing Edge AI and autonomous machines is balancing size, weight, power, and cost (SWaP-C) requirements. NVIDIA’s newest embedded platform opens possibilities for AI projects with unparalleled size vs. power capabilities. Join Connect Tech and NVIDIA’s embedded experts to learn more about specific use cases, how to accelerate development (and deployment) of …

Tessent DDYA – Improving the throughput of volume scan diagnosis by 10X using dynamic partitioning

Register For This Web Seminar Online - Jul 14, 2020 5:00 PM - 6:00 PM US/Pacific Register Online - Jul 15, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Learn how to achieve efficient utilization of hardware resources for volume scan diagnosis. This web seminar will be conducted by an expert in design-for-test and …

Valor Process Preparation Webinar – A Single Engineering Solution

Register For This Web Seminar Online - Jul 15, 2020 11:00 AM - 12:00 PM US/Pacific Register Overview Valor Process Preparation - A Single Engineering Solution for PCB Assembly and Test Electronics manufacturers typically have a silo system in which they perform the PCB assembly process engineering. The main challenge working with a separate system …

Asynchronous Circuit Design for Reliability and Security

Presented By: Dr. Jia Di, University of Arkansas Webinar Description Invented back in 1950’s, asynchronous circuits have not been developing nearly as fast as their clocked, synchronous counterparts. While the synchronous design paradigm dominates the current digital IC market, there are many applications for which asynchronous circuits have unmatched advantages. This is due to their …

Multi-Layer Capacitor (MLCC) Loss

Presented by: Istvan Novak In power distribution networks (PDN), capacitors are used in the largest number. Real-life capacitors always have parasitic resistance and inductance and those values are not guaranteed by the vendors, but capacitance is a guaranteed parameter. Surprisingly, however, many modern high-density ceramic multi-layer capacitor (MLCC) may have a huge loss of their …