About the Event The Second Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions …
Day One - February 7 With the growing pervasiveness of artificial intelligence and machine learning (AI/ML), photonics is playing an increasingly important role in enabling AI transformation. We all know …
Continue reading "Cadence Workshop: The Rise of Photonic Computing"
In a world where the chiplet market is projected to soar to $50.5 billion in revenue by 2024, staying ahead of the game is crucial. This monumental shift in the …
Continue reading "Webinar: The Perfect Duo: Chiplet Design Meets Modern Data & IP Management"
In this webinar, we'll explore the complexity of optical properties that Speos can handle and how these can be fully measured. Our partner, Opsira, will present their hardware and service …
Continue reading "Webinar: How to Get the Highest Quality Material Data for Speos"
Thursday, February 8, 2024 | 9-10 a.m. PT The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There …
Continue reading "Webinar: Addressing UCIe 1.1 IP and System Level Verification Challenges"
Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment can uncover SI/PI issues early …
