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Webinar: Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis

February 8 @ 10:00 AM - 11:00 AM

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Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment can uncover SI/PI issues early in the design process, leading to faster signoff of designs. With analysis shifting left in the design cycle, design teams can achieve efficient signoff of high-speed PCB designs that include complex power delivery networks, gigabit-speed serializer/deserializer (SerDes), and the latest double-data rate (DDR) memory interfaces.

Learn about three key issues that engineers must overcome to sign off on high-speed PCB designs: serial link compliance (SerDes), power analysis, and DDR memory interface compliance. We will demonstrate how Cadence’s PCB design methodology, including Sigrity Aurora, Sigrity SystemSI, and Allegro technologies, empowers EEs to create successful products on time and on budget.

Attendees will learn to address: 

  • SerDes compliance
  • Power analysis
  • DDR memory interface compliance


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