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Webinar Series: Digital Implementation and Machine Learning

June 24, 2020 @ 3:00 PM - 4:00 PM

Webinar Series

Webinars are chosen during registration

Digital Implementation Flow Automation and Vivid Design Metrics Visualisation

June 10, 2020; 15:00 (UKT) 16:00 (CEST) 17:00 (EEST/IDT)

Speaker: Benoir Carpentier

Creating a final design is a sequence of operations from RTL synthesis, through implementation to sign-off. Each of these operations is further split into different steps, such as placement, clock tree synthesis, and routing. When run as part of a typical design flow, these steps generate a vast quantity of valuable data, which can help users better understand the design Cadence provides a flow automation utility called FlowKit, which enables a user to quickly capture and execute any desired sequence of operations. In addition,  the Vivid Metrics infrastructure allows design data to be captured as the flow runs, and then visualized using a web browser. Attend this webinar to learn how to use Cadence® FlowKit and Vivid Metrics to improve productivity.

Webinar Agenda:

  • Cadence Stylus technology overview
  • Capturing a design flow with FlowKit
  • Using FlowKit to manage and execute design runs
  • Vivid Metrics to visualize design data
  • Q&A session

Innovus Hierarchical Flow Overview and New 20.1 Features

June 17, 2020; 15:00 (UKT) 16:00 (CEST) 17:00 (EEST/IDT)

Speaker: Stefano Piccioni

Today´s most advanced semiconductor designs targeting automotive, mobile, hyperscale, and AI/ML applications are pushing into hundreds of millions and even billions of instances, requiring a coordinated hierarchical strategy. This webinar provides a technical overview of the Cadence® Innovus TM Implementation System´s hierarchical design solution for managing large SoC implementation while mitigating schedule risks. A Cadence technical expert will walk through the hierarchical design flow and cover all major steps including partitioning, flexible block modelling and abstraction, pin assignment/feedthrough, timing budgeting, and final chip assembly. Additionally, the latest Innovus 20.1 features and improvements will be highlighted, including early hierarchical floorplan synthesis, and hierarchical database innovations.

Whether you’re new to hierarchical design or an experienced Innovus user, you’ll takeaway hands-on best practices and useful information for each of the topics covered.

Webinar Agenda:

  • Innovus hierarchy introduction
  • Block modelling and timing abstraction
  • Top level partitioning and time budgeting flow
  • Top level assembly and design closure
  • Early hierarchical floorplan synthesis technology
  • Hierarchical and distributed database innovation
  • Q&A session

Extending Power, Performance, and Area (PPA) Using Machine Learning

June 24, 2020; 15:00 (UKT) 16:00 (CEST) 17:00 (EEST/IDT)

Speaker: Kam Rayet

Advanced-node devices are growing in size and complexity at an ever-increasing rate, so designers require new ways to meet their demanding power, performance and area (PPA) goals. Cadence has integrated innovated machine learning technology into the latest implementation flow to enable better quality of results in less turn-around time (TAT). During this webinar we will explain how machine learning is being used as part of InnovusTM Implementation, and for automated digital flow optimization. Join this session to learn more about machine learning technology and how to leverage these innovations to improve your digital design.

Webinar Agenda:

  • Overview of machine learning technology
  • Machine learning inside Innovus implementation, enabling better PPA
  • Automated machine learning digital flow optimization reducing TAT
  • Example results from machine learning
  • Q&A session
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