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Webinar: Latest Techniques for Simulating Calibrated Circuits
Calibration and digital correction methods are routinely applied to overcome sources of variation or to compensate the performance of mixed-signal circuits. Calibration may be performed one time in the lab or may be implemented on-chip as part of a built-in self-test or continuous background calibration. When simulating calibrated circuits, first the calibration procedure is simulated (or emulated), then the correction is applied to the design under test (DUT). Depending on the calibration methodology, the simulation and analysis scenarios and requirements will vary. All of these analysis scenarios are possible using Cadence® Virtuoso® ADE Assembler.
This CadenceTECHTALK webinar describes techniques for simulating calibrated circuits using Virtuoso ADE Assembler. After reviewing the essential features for calibration (for example, the usage of the calcVal() function, Pre-Run OCEAN Scripts, and Run Plans), we will demo various calibration scenarios, such as calibration with Monte Carlo analysis and calibration with binary search.
Date and Time
Wednesday, November 25, 2020
9:00am GMT / 10:00am CET / 11:00am Israel / 2:30pm India
Can’t make the scheduled time? Register, and we’ll send you the recording of the complete webinar you missed.