Webinar: Investigating and Improving Clock Delays

Overview

As typical system-on-chip designs grow larger and move to the latest FinFET process nodes, clocking constraints become ever more complex. The Cadence® Innovus™ Implementation System’s CCOpt™ useful skew optimization engine is a powerful tool to close the timing on the latest high-speed designs. Understanding and managing insertion delay is an important part of clock tree insertion. Please join this free one-hour webinar to learn some advanced CCOpt techniques. This webinar will explain how to investigate and improve clock insertion delays during the CCOpt process.

Date and Time

Sunday, May 31
Time: 14:00 (Israel Daylight Time)

Agenda

· CCOpt debug methods using log file information, GUI, and reports

· Address insertion delays in complex SoC

· Address insertion delays in high-performance designs

This webinar is intended for Cadence customers who have access to the Digital Implementation flow.

*This Webinar will be presented in Hebrew