Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.

Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow, analysing differences between original RTL and ECO RTL, generating patches, and validating changes. Formality ECO also supports aggressive RTL optimization techniques, including retiming and auto ungrouping, while providing advanced analysis and debug features to streamline the ECO process.

In this presentation, we will explore the advantages of Synopsys Formality ECO on the overall ECO cycle including enhanced patching and faster verification runtime leading to improved TAT.