Tackling Advanced Analog FinFET Back-End Layout Challenges with Better Methodologies

Overview

The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider, and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate to longer layout turnaround times and reduced productivity.

This CadenceTECHTALK^™ will focus on silicon-proven technologies that improve layout engineering productivity and efficiency. It is ideal for layout designers and recommended for CAD and analog engineers.