Stratus HLS (High Level Synthesis) Seminar Series: [Part 4] Result analysis and microarchitecture exploration

Date and time: October 13, 2023 (Friday) 15:00-16:00

Sponsor: Japan Cadence Design Systems, Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

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Registration deadline: October 12th (Thursday) 16:00

[Event overview]

In recent years, as LSI designs become larger and more complex, many developers are seeking greater design efficiency and are moving to more abstract design environments.

Since its release, Cadence’s high-level design and verification environment solution Stratus High-Level Synthesis (HLS) has been used by many customers around the world.

This time, we will be holding a webinar series to explain the basics of high-level design, implementation in RTL, and solutions related to its verification.

A total of 5 webinars will cover topics such as the basics of high-level synthesis, SystemC, how to use high-level synthesis, and verification after RTL synthesis.

For those who are interested in high-level design, those who are considering introducing high-level design, and those who want to increase their knowledge, this is a good opportunity to learn what HLS is.
Please join us for this webinar series.

In “[Part 4] Result analysis and microarchitecture exploration”, we will understand the application flow of high-level synthesis and look at how to improve the quality of the final RTL.

In this part, we will explain the high-level synthesis flow and its synthesis result analysis and feedback methods, and will demonstrate the synthesis cycle that generates different RTL from one design input and the method of analyzing the results after synthesis. I will also explain it to you.