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Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging

September 15, 2023 @ 3:00 PM - 4:00 PM

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Date: September 15, 2023 (Friday) 15:00-16:00


Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: September 14th (Thu) 16:00


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In recent years, LSI design has become larger and more complex, and many developers are seeking to improve design efficiency and are moving to a design environment with a higher degree of abstraction.

Cadence’s high-level design and verification environment solution Stratus High-Level Synthesis (HLS) has been used by many customers around the world since its release.

This time, we will be holding a webinar series that will explain the basics of high-level design, implementation in RTL, and solutions related to verification.

A total of 5 webinars will explain the basics of high-level synthesis, SystemC, how to use high-level synthesis, and verification after RTL synthesis.

For those who are interested in high-level design, those who are considering introducing high-level design, and those who want to increase their knowledge, this is a good opportunity to learn what HLS is.
Please join us for this webinar series.

In “[Part 2] SystemC simulation and debugging”, what kind of description is high-level about SystemC, a C language-based high-level synthesis input language introduced in “[Part 1] Learn the basics of high-level synthesis”? Learn what you need when synthesizing.
SystemC is also used during verification and can be seen in a demonstration using Cadence’s simulator, Xcelium.

In this volume, we will explain the main SystemC language descriptions used in high-level synthesis and various methods for design verification.


Akira Fujita , System  & Verification Application Engineer, Field Engineering & Service Division, Cadence Design Systems Japan 

Stratus HLS (high-level synthesis) seminar series planned

[Part 1] Let’s learn the basics of high-level synthesis: Thursday, August 31, 15:00-16:00 

The schedule for [Parts 3 to 5] will be announced at a later date.


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