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Stratus HLS (High Level Synthesis) Seminar Series: [Part 1] Let’s learn the basics of high-level synthesis
August 31 @ 3:00 PM - 4:00 PM
Date: August 31, 2023 (Thursday) 15:00-16:00
Organizer: Cadence Design Systems Japan, Innotech Co., Ltd. IC Solution Division
Venue: Online (Zoom webinar)
* It is also possible to participate from a web browser.
We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: Wednesday, August 30, 16:00
In recent years, LSI design has become larger and more complex, and many developers are seeking to improve design efficiency and are moving to a design environment with a higher degree of abstraction.
Cadence’s high-level design and verification environment solution Stratus High-Level Synthesis (HLS) has been used by many customers around the world since its release.
This time, we will hold a webinar series that will explain the basics of high-level design, implementation in RTL, and solutions related to verification.
A total of 5 webinars will explain the basics of high-level synthesis, SystemC, how to use high-level synthesis, and verification after RTL synthesis.
For those who are interested in high-level design, those who are considering introducing high-level design, and those who want to increase their knowledge, this is a good opportunity to learn about what HLS is.
Please join us for this webinar series.