Side-Channel Leakage Assessment of Cryptographic Modules

Presented By: Dr. Jungmin Park, University of Florida

Short summary

Side-channel attacks (SCAs) such as simple power analysis (SPA), differential power analysis (DPA) and correlation power analysis (CPA) have been proven to be effective to extract secret keys from hardware implementations of cryptographic algorithms. These attacks are based on the dependency between intermediate data related to the secret key and power consumption. In order to prevent SCAs, most of countermeasures remove the dependency by randomizing the intermediate values or obfuscating power consumption.

Due to the risk of SCAs, side-channel leakage assessment of the hardware implementations has become very important and the cryptographic implementations at the post-silicon stage have been evaluated by general side-channel leakage tests such as CRI’s TVLA, mutual information test, KL-divergence test or SCAs. In addition, the cryptographic design should be evaluated at early design stages (e.g., RTL and gate level) to reduce design costs.

In this talk, I will introduce how to analyze and quantify side-channel leakage information at various design stages such as RTL, gate level and post-silicon level. Based on these analysis, most vulnerable modules will be searched and replaced with secure modules.

Intended Learning Outcomes (ILOs)

Upon the completion of this webinar, trainees should be able to:

• Understand the basic principles of SCAs
• Understand how to evaluate side-channel leakages at various design stages
• Understand the basic principles of side-channel countermeasures

Target Audience

Design engineers, senior undergraduate students and graduate students who are interested in understanding power/EM side-channel attacks, side-channel evaluation and side-channel countermeasures.

Short Bio

Jungmin Park is currently a Research Assistant Scientist at the Florida Institute for Cybersecurity (FICS) Research, University of Florida, Gainesville, USA. He received his Ph.D. in computer engineering from Iowa State University, Ames, IA, in 2016. His research interests include side-channel disassembly, side-channel attacks (SCAs), SCA resistant hardware design, quantum random number generator, and hardware Trojans.