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Leveraging HLS IP to Accelerate Design and Verification

October 22

Register For This Web Seminar

Online – Oct 22, 2019
10:00 AM – 11:00 AM US/Pacific

Overview

To accelerate and ease the adoption of HLS, Catapult provides both building block HLS IP and various application reference designs written in C++ or SystemC that are designed to help deliver optimal QofR. This webinar will describe the available IP including the Math and DSP blocks available as open-source and the several reference designs, including 2-D convolution for image enhancements and two CNN (tinyYOLO) implementations for real-time object classification.

This webinar is part 5 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators

What You Will Learn

  • How HLS is used to implement a computer vision algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
  • How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
  • How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
  • How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
ABOUT THE PRESENTER
David Burnette

David BurnetteDavid Burnette is currently Director of Engineering for the Catapult High-Level Synthesis product of Mentor, a Siemens Business. He has contributed to the HLS program over the last 26 years, starting first with behavioral synthesis from VHDL followed by C++/SystemC. Much of his recent work has centered around High-Level Verification (designing infrastructure for comparing the untimed C++ against the timed RTL) and the development of class-based C++ HLS IP for math, DSP/Image Processing and Machine Learning. He received his BSEE and MSEE from Virginia Tech and holds 4 patents in the area of HLS methodologies.

Products Covered

Who Should Attend

  • RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
  • Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
  • New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.