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IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
November 2 @ 10:00 AM - 5:00 PM
Date: November 2, 2023
Time: 10:00am – 5:00pm
Location: Cadence Headquarters, San Jose, CA | Building 5 – Big Sur
Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis.
As a leading-edge chip designer, do you frequently find yourself with too many IR violations to be fixed at the signoff stage? They might require a long time to fix the violations or even waive them, increasing the turnaround time or risk of failure. To meet these challenges, we need new analysis methods like hierarchical analysis, incremental IR drop analysis, early prototyping, optimization of power networks for chiplets and 3D-ICs, as well as new methods of design coverage. In addition, we need a “shift left” strategy enabled with AI that can integrate PI in the implementation process to identify, automatically diagnose, and fix PI problems efficiently, leaving little room for surprise at signoff.
Join us at our CadenceCONNECT event and learn from technical experts in academia, foundries, the design community, and Cadence on how we are addressing these PI challenges.
The seminar is free and open to technical experts and managers involved in physical design implementation and silicon signoff. Lunch and snacks are provided.