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Interactive (Live Simulation) Debug Techniques for UVM, SystemVerilog and RTL using Visualizer Advanced Debug GUI

October 27

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Online – Oct 27, 2020
8:00 AM – 9:00 AM US/Pacific
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Overview

Need to quickly understand what is going on in a new simulation environment?

Trying to figure out why the data in your UVM scoreboard doesn’t match what it was expecting?

Don’t have the visibility that you need from your overnight simulation runs?

Debug is one of the most time consuming tasks verification engineers face in the design and verification of FPGAs, IPs and SoCs.  Visualizer provides an advanced debug environment that includes many tools to help with both post-simulation and live-simulation debug.

This session will focus on live-simulation (interactive) debug, covering techniques such as:

  • Setting breakpoints and stepping through source code
  • Using the call stack to understand the current thread of execution
  • Viewing SystemVerilog class data and local variables alongside RTL signals
  • UVM testbench debug, including UVM Phases, Sequences and Registers.

What You Will Learn

  • Using breakpoints and stepping through source code to understand behavior
  • Using the call stack to understand the current thread of execution
  • How to view SystemVerilog class data and local variables alongside RTL signals
  • Techniques for UVM testbench debug, including UVM Phases, Sequences and Registers
  • How to understand testbench memory use and find memory leaks
ABOUT THE PRESENTER
Jason Polychronopoulos

Jason Polychronopoulos
Jason Polychronopoulos is a Product Engineer at Mentor, A Siemens Business, specializing in Visualizer and Questa simulation. He has 20 years of experience in functional verification, verification tools, methodologies and design of verification IP. Mr. Polychronopoulos holds a Masters in Electronic Engineering from The University of Manchester.

Who Should Attend

  • IP, FPGA and SOC Design & Verification Engineers
  • Engineering Managers

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