Improved Debug and Package Handling for Mixed-Signal Verification

Mixed-signal simulations have unique challenges whether you’re running from the command line or within the Cadence® Virtuoso® platform. Where are the interfaces between logic and electrical and are they behaving correctly? How do you visualize the analog and digital blocks of the design? Are the models and testbench components incorporated correctly in the simulation? How much current is being drawn in different sections of the design? Join us to learn ways to tackle these challenges.

Learn how to:

• Identify and debug interface elements between analog, digital, and real signals
• View electrical and logic portions of the design using Cadence’s SimVision™ Debug Schematic Tracer
• Import SystemVerilog models, packages, and testbenches into the Virtuoso platform for mixed-signal simulation
• Interactively probe analog currents during mixed-signal simulations

Date and Time

Wednesday, February 17

EMEA and India: 09:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 India

North America: 10:00am PST / 1:00pm EST