From MATLAB® to High-Quality RTL Using High-Level Synthesis — The Design Methodology

Overview

MATLAB^® is a de facto standard algorithm development tool in many image and signal processing hardware designs. Yet, the traditional path from an abstract floating-point MATLAB model to high-quality RTL code is long and often requires multiple manual coding stages, several designers and many code bases to be maintained.

This process can be simplified by using Catapult^® High-Level Synthesis (HLS) along with a sophisticated workflow. The model transformation from MATLAB to class-based C++ is much simpler than transformation from MATLAB to RTL because the abstraction level can be kept high.

Using a systematic data type definition scheme, the conversion to fixed-point can be done in C++ using the same functional C++ code for both floating-point and fixed-point implementations. This reduces the number of code bases to be maintained down to two: one MATLAB and one C++ model that can be automatically validated.

The whole process can be completed by 1-2 designers in a short time resulting in similar or even better power, performance and area metrics compared to a hand-coded implementation.

This webinar introduces a design methodology that starts from a self-contained MATLAB script and goes through the different workflow steps to HLS generated, high-quality RTL. All design steps including fixed-point conversion are described in detail.

What You Will Learn

• MATLAB to RTL methodology overview
• Model analysis, data type extraction and HLS structure planning
• Fixed-point analysis basics
• Validation of C++ model in MATLAB
• Step-by-step walkthrough of the workflow

ABOUT THE PRESENTER

Petri SolantiPetri Solanti is a senior application engineer at Mentor, A Siemens Business, with an HLS and low-power tools focus. He is a designer and application engineer with over 25 years of experience in Electronics System-Level design tools and methodologies. His areas of interest include design methodologies from algorithm to RTL, system analysis and HW/SW co-design. Prior to Mentor, Mr. Solanti held application engineer positions at Cadence, CoWare, Synopsys and MathWorks. He received his MScEE degree from Tampere University of Technology, Finland.

Who Should Attend

• Engineering Directors who need faster design cycles and lower verification costs than RTL design provides
• RTL Design and verification managers who need to improve team productivity
• RTL Designers concerned that RTL might no longer be enough to compete
• System Architects looking for optimal design partitioning for power, performance and area
• Algorithm Developers who are interested in HW bottlenecks in their algorithm

Products Covered

• Catapult HLS