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Error Reduction in the Design Definition Phase
June 16 @ 2:00 PM - 3:00 PM
Schematic entry sounds like a simple task. But the simple and often obvious errors are the ones that cause major delays: wrong or forgotten voltages, wrong termination, flipped diodes, miscalculated driver strength are only a few of the typical issues. As a result 3 out of 4 projects require changes and respins that can be costly and cause delay of the product. Getting things right the first time requires different approaches. And while checking for these possible errors is already challenging for a single board, wait until you need to check across your multi-board system.
Instead of focusing on the functionality intent, design reviews are focusing on finding these kind of issues. But there are methods available that allow you to eliminate these errors programmatically, so you can focus on the essentials.
During this webinar we will be showing approaches to reduce errors in the design definition phase, reducing risks and overhead during schematic reviews.
What You Will Learn
- Most commonly found glitches in schematics
- Electrical and logical issues that could be prevented easily
- How to avoid spending unnecessary time on checking schematic integrity
- Application of automated, rule based tools and interpretation of reports
- Avoiding unnecessary review time by reducing false positives
- Scaling your validation efforts from single boards to systems
- Addressing modeling needs for integrity checks
Nicole KyleNicole is a Technical Marketing Engineer for the Electronic Board Systems group at Mentor, A Siemens Business. She started at Mentor as an Associate Rotation Engineer, and has worked with front-end design products in the Xpedition flow for over three years. Nicole is a graduate of Harvey Mudd College with a Bachelor’s of Science degree in Engineering.
Who Should Attend
- Electrical Engineers
- System Designers and Integrators
- Engineering Managers
- Project Managers