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Debugging Features of UVM
June 15 @ 10:00 AM - 11:00 AM
A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging.
There are various debugging features built into UVM to help with this. In this webinar Doulos Senior Member Technical Staff, Doug Smith, explores the various features in UVM to help you debug your UVM environment, your test cases, and your design under test.
- Debugging the Testbench
- Debugging Stimulus
- Debugging the Design
At the end of the webinar Doug will also look at some of the tool support features for debugging UVM using Cadence® Xcelium™ Logic Simulation.Share this post via: