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Co-Simulation-Enabled “Thermal-Aware” Power Signoff for System Design

June 18, 2020 @ 11:00 AM - 12:30 PM


Can you risk the thermal performance of your next design to the constraints of the simplified models across multiple tools for a thermal signoff ?

Don’t miss out on the chance to hear what Celsius™ Thermal Solver, the only solution that can perform static and dynamic thermal analysis and electrical-thermal co-simulation across chip, package, PCB, and enclosure. All of that comes with its massively parallel architecture, which is based on the proven computational software technology by Cadence, delivering 10X speed-up with gold-standard accuracy and unlimited scalability.

In this free webinar, our expert will discuss:

  • Thermal challenges in electronic system design
  • Importance of transient and steady-state electro-thermal analysis
  • Concepts: Heat transfers, thermal resistances, BC’s and thermal cooling
  • Small ICs to large chassis by 10X speed with multi-core parallelization
  • Chip-package-board-chassis thermal and power signoff analysis

Date and Time

Thursday, June 18, 2020
Time: 11:00 am – 12:30 pm (India Time)

Please Note:

  • Registration closes at 10:00 pm on Wednesday, June 17, 2020.
  • If you register, please plan on attending.

For questions and inquiries, or issues with registration, send an email to india_events@cadence.com

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June 18, 2020
11:00 AM - 12:30 PM
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