CDC Workshop: “Hierarchical CDC and RDC Closure with Standard Abstract Models”

Accellera at DVCon US 2024

Abstract:

As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. We will then discuss the hierarchical CDC/RDC verification methodology, the tradeoffs faced when incorporating units from multiple sources, and the challenges when integrating multiple vendor-generated abstracted blocks into an encompassing design. To mitigate these issues, we introduce the Accellera CDC committee, highlight the released CDC standard, and summarize the status of the current efforts.

Topics:

• CDC-RDC Basic Knowledge
• Clock domain crossing schemes
• Reset domain crossing schemes
• CDC-RDC Verification
• Hierarchical CDC Verification
• Accellera CDC Working Group

Speakers:

• Ping Yeung, Nvidia
• Iredamola Olopade, Intel
• Kranthi Pamarthi, Renesas Electronics
• Chetan Choppali Sudarshan, Marvell Technology
• Farhad Ahmed, Siemens EDA
• Bill Gascoyne, Blue Pearl
• Anupam Bakshi, Agnisys

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