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CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA

January 21

Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.

CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA will introduce you to optimized design methodologies for the Arm® Cortex®-X1 and Neoverse™ processors. The event brings together Cadence® and Arm technology users and experts to learn more about how you can efficiently implement your Arm-based SoCs with the Cadence digital full-flow solution and reach your power, performance, and area (PPA) targets. Join us to learn about the latest Arm and Cadence collaboration from experts in each area, with live Q&A after each presentation.

Agenda

Times listed in agenda are Pacific Standard Time

8:00am PT, 11:00am ET, 4:00pm GMT, 5:00pm CET

08:00am PT – Arm Keynote – Collaboration in a time of change (Dermot O’Driscoll, VP Product Solutions, Infrastructure)

08:20am PT – Cadence Keynote – Building Arm Total Compute for Optimal Performance Within Power Budgets (Yufeng Luo, VP Research & Development)

08:40am PT – How We Pushed Largest 5nm High-Performance Arm Core to 4GHz Frequency

09:10am PT – Divide and Conquer:  Hierarchical Methodology to Reduce TAT by 30% or More on Arm’s High-Performance CPU

09:40am PT – Delivering Best-in-Class Low Power for Arm Cortex-A78 Mobile 7nm CPU Using the Cadence Digital Flow

10:10am PT – Arm Neoverse CPU Advanced Timing Signoff with Tempus™ PI Technology

10:40am PT – Cloud-Based Characterization with Cadence Liberate™ Trio Characterization Suite and Amazon EC2 M6g Instances Powered by Arm-Based AWS Graviton2

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Date:
January 21
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Cadence
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