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Arm and Cadence: Achieving Best Silicon Power, Performance, and Area
Join Cadence and Arm to learn how you can achieve the best power, performance, area (PPA) and time to tapeout for Arm® CPU implementation using the latest Cadence® Digital Full Flow. This event covers topics including high-performance design for the Arm Cortex®-A710 and other Arm processors, energy-efficient CPU implementation flows, high-reliability design using Arm library IP, and aging-aware static timing analysis (STA). This is a great opportunity to benefit from the long and extensive engineering collaboration between Arm and Cadence to accelerate your SoC projects.