While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.
The two speakers were:
Department Manager, Design Methodology & Service Marketing Program R&D, TSMC
Dr. Tong Gao
First up was Willy Chen from TSMC presenting the foundry challenges at 20nm.
- 28nm doesn’t use double patterning litho
- 20nm will use double patterning (DPT)
Four Vertical lines are separated into two pairs of lines, forming Double Patterning
Double patterning poses issues when spacing is too close on the same layer, so your EDA tool has to account for these DPT rules. The challenge is that not every layout pattern can be separated into two mask sets, so TSMC has created something called the G0-Rule to let you know if your layout can be separated.
Using two masks per layer can create RC variations in your IC design, so you have to run more Static Timing Analysis (STA) runs. EDA tools will have to use multi-value SPEF files instead of single-value SPEF files.
DFM (Design For Manufacturing) LPC (Litho Process Check) requires new hot spot checks and spacing checks, and they call it coloring:
Designers don’t have to worry about which layout shapes go to each double pattern per layer because pre-color can be used. Mask alignment variation will effect sensitive nets like inputs to a differential pair, clock net, or bit lines of a memory.
Pre-color for APR is still in development, stay tuned for final details.
Early collaboration is more critical at 20nm between TSMC, EDA and IC designers. This is the earliest webinar for 20nm technology.
Most EDA tools need modification for 20nm IC design.
- Phase 1: P&R, DRC, LVS, RC Extraction, Custom Design (basic)
- Phase 2: STA, IR, EM, Custom Design (advanced)
EDA tool certification will happen in phases for 20nm, so Phase 1 certification based on V0.1 design rules and SPICE models is completed for: DRC, LVS, RCX, P&R, Custom Design (basic). Pre-coloring will be addressed in V0.5 certification, then all EDA tools will be ready by V1.0 certification.
Tong Gao from Synopsys presented next.
20nm should be in production by 2014. 14nm initial starts in 2014 also.
20nm has an increase in manufacturability issues, mostly met through DPT where geometries on a single layer are split up into two masks by EDA tools.
Whats needed at 20nm is concurrent closure of: Power & Performance, Manufacturability, Throughput.
Synopsys Galaxy tools are being updated to deal with DPT effects.
IC Compiler (Place and Route) is being updated to use DPT.
IC Validator (DRC and LVS) is being updated to enable DPT compliance.
IC Compiler has already had a 20nm tapeout test vehicle. This tool exploits multi-core to help reduce turn around times.
Leakage power reduction is achieved using libraries with multiple Vt choices. Example designs show between 5% and 25% leakage reduction using multiple Vt libraries.
Optimal placement of registers on the layout help balance the interconnect delays and therefore improve timing.
Multisource clocks can offer low skew than CTS, better On Chip Variation (OCV), less power than clock mesh, and greater clock gate depth than clock mesh.
Design Planning has been improved by 1.5X in the past year.
Your IC layout libraries need to be made DPT ready. Things to avoid: jogs on odd pitches.
Cell placement needs to be DPT aware to avoid errors.
Routing is really impacted most by DPT requirements. Choice one is the most efficient DPT clean solution.
Most layout routing can be automatically decomposed to be DPT clean.
Even pitch jogs are preferred, odd-pitch jobs should be avoided.
Synopsys has run a 20nm ASIC design through: DPT compliant standard cell placement, DPT aware routing, DPT compliance in Proteus:
If your IC layout has any DPT related issues then you will get a warning in the IC Validator GUI:
Automatic Design Repair (ADR) – can fix some DPT violations.
A version 0.5 and 1.1 design flow are to be done in collaboration between TSMC and Synopsys.
Q: What are the key benefits of migrating to 20nm?
A: Higher gate density improvement, like 2X. Speed improvement of 20% at 0.85V. 25% lower power.
Q: Is pre-coloring necessary?
A: Yes, it is needed for sensitive nets like sense amp inputs and word lines in RAMs. Synopsys will support pre-coloring requirements. It will cost you in routing times and area.
Q: What is the run-time impact on the physical flow?
A: Expect to see small run-time requirements, although your routing results will vary from before. DRC convergence time will increase. Turning on DPT requirements are at least 10 to 20% for easy convergence, while other designs are more difficult.
Q: Which layers will require DPT at 20nm?
A: Diffusion layer and lowest metal layers, design dependent.
Whew, 50+ slides in 50 minutes, now that was flying.
To print your IC layout on a wafer at 20nm requires ever more restrictive layout design rules, and at 20nm the introduction of DPT will be applied to several layers. EDA tools are being re-tooled to cope with the DPT issues, however you will see longer tool run times and new steps added to your design, analysis and layout methodology.
With only a 20% speed improvement expected going from 28nm to 20nm, you need to decide if the 25% lower power and up to double the gate count is viable for your new SOC designs.Share this post via: