Logic Synthesis Reborn

Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write software that can handle larger designs, in a shorter amount of time, with better PPA (Power, Performance, Area) results?

Logic synthesis is a workhouse EDA tool that converts a design written in languages like SystemVerilog and VHDL into technology-specific gates that are logically optimized and take into account physical effects like interconnect estimates. The design process with logic synthesis is quite iterative, so any improvements in run time, capacity and PPA make a big difference to product schedules.

What’s New

The trend over at Cadence and other EDA vendors is to rewrite their code in order to meet these increasing market challenges. Paul Cunningham of Cadence spoke with me last week about a new logic synthesis tool called Genusthat is the successor to RTL Compiler. The benefits of using the new Genus tool for logic synthesis are:

• Speed, up to 5X faster than RTL Compiler
• 2X fewer iterations at unit-level
• Timing and wire length estimates are within 5% of Innovus place & route
• Smaller area and lower power on datapath, up to 20%

How it Works

A new logic synthesis architecture was selected that uses a massively parallel approach, with multiple machines and CPUs, while being timing-driven. Your design is automatically partitioned into smaller instances, split up across multiple machines and CPUs, exploiting multi-threading, then balancing the load between machines and CPUs through adaptive scheduling.

Results

If you are an RTL Compiler user today and switch to Genus then expect run-time improvements between 3X to 5.5X, now that’s a huge gain. Capacity is impressive with Genus, so a design with 34M cell instances will run logic synthesis on 16 machines with 4 CPUs each in 2 days, something that you couldn’t do with RTL Compiler.

The next tool run after logic synthesis is place and route, so following Genus you can run the Innovus place and route tool for an all-Cadence flow. These two Cadence tools share code for:

• Parasitic extraction
• Delay calculation
• Global routing
• User interface

Related – Cadence’s New Implementation System Promises Better TAT and PPA

Benefits of this unification are that you can expect 4X faster routing times compare to using the Encounter Digital Implementation System, and that the timing and wirelength calculations are within 5% meaning quicker timing closure. If you have the Synopsys ICC2 tool for place & route, then you can use Genus for logic synthesis as well.

The two new Cadence tools Genus and Innovus will out-perform the previous generation tools RTL Compiler and Encounter Digital Implementation System. Here’s a table comparing timing and wirelength results between the old and new generation of tools:

RCP – RTL Compiler, EDIS – Encounter Digital Implementation System

Another part of the secret-sauce inside of Genus is how it does architecture-level PPA optimization by characterizing different architectures and then analytically solving for the best solution.

Datapath designs will see improvements with Genus, and one customer design using a datapath inside of a video codec showed an area reduction of 16% while meeting the timing specs, while running 2.3X faster.

Related – High Level Synthesis Gets Stronger

Summary

It’s quite natural for new technology to replace old as the design challenges increase, and in EDA this means that Cadence has a new generation of logic synthesis tool in Genus that raises the bar in our industry. Engineers at TI found that Genus produced results 5X faster, and Imagination Technologies used this new logic synthesis tool on their PowerVR GE7800 GPU.

Users of RTL Compiler can try Genus without making any changes to existing scripts, so there’s no learning curve. If you’re looking at Genus and have no RTL Compiler experience, then expect a learning curve of just a few days.