In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently had the opportunity to speak with these two gentlemen again. This time, we explored the new 20.1 release of the Tempus Timing Signoff Solution in terms of its ability to deliver faster timing signoff with optimal PPA results. Once again, I was impressed by the information they provided, this time about how they are addressing the customers’ time-to-market constraints.
We began our discussion with a review of the design challenges and customer requirements. It’s well-known that design and modeling complexity are increasing at advanced nodes; and while the competitive marketplace demands higher performing devices (for longer battery life, faster compute, etc.) the time-to-market window for these devices continues to shrink. Hitendra presented a very concise summary of all these forces, included below. I haven’t seen such a coherent view like this before—it’s worth a look.
In order to address time-to-market challenges, it’s clear that the following five items, in order by priority level, are the key customer requirements:
- Fewest iterations
- Optimization/the best PPA
- Fastest design closure
- World-class support
Hitendra and Brandon then went into several dimensions of the 20.1 Tempus release, which address these customer requirements while dealing with the myriad of challenges listed above. I’ll provide a short summary of each dimension here. It’s how Cadence delivers faster timing signoff with best-in-its-class PPA, but above all, it reduces the customers time-to-market challenges.
Integration with the Innovus™ Implementation System
The integration between various signoff quality engines at Cadence has served them well. With this integration, Cadence provides an ECO flow that is physically aware and embeds the power of path-based analysis inside the digital full flow. This seamless integration puts signoff-quality timing and power analysis in the hands of the place-and-route engineer.
As a result of the integration, engineers can achieve higher-quality block-level implementation and smoother signoff at the chip level. One can achieve 2X faster convergence with improved PPA. For example, Renesas presented their results using Tempus ECO at CadenceLIVE. They reported a designer time/effort reduction of 50% with a 10% power reduction as well. It’s not surprising that approximately 80% of Innovus customers are using Tempus ECO.
Cadence has multiple initiatives to utilize machine learning (ML) techniques to drive runtime and power, performance and area (PPA) gains throughout its product lines. In the case of Tempus ECO, Cadence utilized an “ML outside” application in Cadence-speak to “learn” from numerous advanced-node designs. By analyzing the various design characteristics (slack, congestion, etc.), Cadence enhanced the optimization algorithms to improve runtime by 2X to 3.5X while still maintaining excellent PPA results.
This technology delivers a rich debugging toolbox through a GUI. Besides improving usability, it’s a key method that allows signoff quality information to be delivered to the place-and-route engineer in an easy-to-understand graphical manner.
C-MMMC stands for concurrent multi-mode/multi-corner static timing analysis (STA). This technology provides a significant speedup in runtime for the analysis of multiple timing views by combining them into a single run. A case study from Inphi highlighted their use of C-MMMC with physically aware ECO to accelerate full-chip closure and signoff by 2X. Impressive.
With the number of views increasing for advanced nodes to 200 or more, it becomes necessary to compact these views to manage turnaround time. SmartMMMC automatically accelerates optimization across a large number of views with virtually no PPA penalty. Designers significantly benefit from this approach because they can more easily close timing across all views in a single optimization pass.
Beyond view count, there are also unique challenges associated with optimization of very large designs. High-capacity ECO enables the efficient optimization of large, full chip designs in a flat, easy-to-use flow. A CadenceLIVE case study from Marvell was discussed. Using this approach, Marvell was able to reduce runtime from 27 hours (traditional hierarchical Tempus ECO) to 5 hours (Tempus full-chip ECO). More impressive results.
Distributed Static Timing Analysis (DSTA)
This one has been around a while but is quite critical to signing off extremely large designs that exist at advanced nodes. Think of performing STA on 300 million to 1 billion instances. Doing this on a huge single machine would be prohibitively expensive whereas distributing the problem across multiple, smaller machines is preferable.
The problem here is partitioning the design in a smart way so that the communication between parallel machines doesn’t negate all the benefits. Cadence has figured out a way to do just that. Given DSTA’s scalable nature, the technology is well-suited to cloud deployment.
So ends another chapter in the Tempus story. I learned enough during my conversation with Brandon and Hitendra to know the story is far from over. There will be more installments. So, this is how Tempus reduces time-to-market challenges and delivers faster timing signoff with optimal PPA results. The key takeaway for me is that the Tempus integration with Innovus is the key driver and concurrent power and timing optimizations produce exceptional results. Also, SmartHub is impressive, enabling designers to quickly converge on their designs as full-chip ECO and DSTA allows faster design closure and shorter turn-around times.
You can learn more about the Cadence Tempus timing signoff solution here.