ECO Demo Update from Easy-Logic

ECO Demo Update from Easy-Logic
by Daniel Payne on 04-18-2024 at 10:00 am

EasylogicECO Design Flow

I first met Jimmy Chen from Easy-Logic at #60DAC and wrote about their Engineering Change Order (ECO) tool in August 2023. Recently we had a Zoom call so that I could see a live demo of their EDA tool in action. Allen Guo, the AE Manager for Easy-Logic gave me an overview presentation of the company and some history to provide a bit of context.… Read More


Shell Eco-marathon Asia-Pacific and the Middle East

Shell Eco-marathon Asia-Pacific and the Middle East
by Admin on 03-25-2024 at 4:00 pm

Regional competitions / July 2-7, 2024

Teams from all over the Asia-Pacific and the Middle East come together in this competition of engineering excellence and energy efficiency.

Keep an eye on this page for more details and updates.

Asia-Pacific and the Middle East region Phase 1 registration: September 21, 2023 – February… Read More


Visit with Easy-Logic at #60DAC

Visit with Easy-Logic at #60DAC
by Daniel Payne on 08-29-2023 at 10:00 am

Easy-Logic at #60DAC

I had read a little about Easy-Logic before #60DAC, so this meeting on Wednesday in Moscone West was my first in-person meeting with Jimmy Chen and Kager Tsai to learn about their EDA tools and where they fit into the overall IC design flow. A Functional Engineering Change Order (ECO) is a way to revise an IC design by updating the smallest… Read More


Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
by Admin on 07-13-2023 at 9:27 pm

Wednesday, July 26, 2023 | 10:00 a.m. – 11:00 a.m. PDT

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased

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Webinar: Fast and Accurate Functional ECOs with Synopsys Formality ECO

Webinar: Fast and Accurate Functional ECOs with Synopsys Formality ECO
by Admin on 08-10-2022 at 4:27 pm

Synopsys Webinar | Tuesday, August 16, 2022 | 8 a.m. Pacific

To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However, during the late-stage functional

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Sign Off Design Challenges at Cutting Edge Technologies

Sign Off Design Challenges at Cutting Edge Technologies
by Tom Simon on 12-03-2020 at 6:00 am

Power and Ground Design Challenges

As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More


Tempus: Delivering Faster Timing Signoff with Optimal PPA

Tempus: Delivering Faster Timing Signoff with Optimal PPA
by Mike Gianfagna on 10-12-2020 at 10:00 am

Tempus Delivering Faster Timing Signoff with Optimal PPA

In July, I explored the benefits of the new Cadence Tempus™ Power Integrity Solution. In that piece, I explored some of the unique capabilities of this new tool with Brandon Bautz, senior product management group director and Hitendra Divecha, product management director in the Digital & Signoff Group at Cadence. I recently… Read More


Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success

Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success
by Admin on 05-26-2020 at 11:38 pm

Overview

As designs grow in complexity, rigorous formal verification is essential to meet aggressive requirements for power, performance, area, and time to market. Equivalence checking, static verification, automated ECO, and constraint design for clock domain crossing (CDC) are some of the challenges that signoff designers

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Leveraging HLS/HLV Flow for ASIC Design Productivity

Leveraging HLS/HLV Flow for ASIC Design Productivity
by Pawan Fangaria on 12-23-2015 at 12:00 pm

Imagine how semiconductor design sizes leapt higher with automation in digital design, which started from standard hardware languages like Verilog and VHDL; analog design automation is still catching up. However, it was not without a significant effort put in moving designers from entering schematics to writing RTL, which… Read More


Synopsys Vision on Custom Automation with FinFET

Synopsys Vision on Custom Automation with FinFET
by Pawan Fangaria on 06-26-2015 at 7:00 am

In an overwhelmingly digital world, there is a constant cry about the analog design process being slow, not automated, going at its own pace in the same old fashion, and so on. And, the analog world is not happy with the way it’s getting dragged into imperfect automation so it can be more like the digital world. True, the analog world… Read More