Variation-aware IC Design

We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, created in December 2012, so I spent an hour today viewing it. Steven Lewis started out the webinar and then Alan Whittaker did a product demo showing how he uses Virtuoso to find and fix LDE issues.

Steve Lewis, Cadence

Alan Whittaker, Cadence

What’s new with LDE is that the IC layout now changes the MOS device parameters like:

• Idsat
• Vth
• gm
• Cgs

These device parameters determine your analog and mixed-signal circuit performance.

The top four LDE are:

As an example, if you did a 20nm IC layout using the minimum distance of an active MOS device edge to the NWell that would trigger the WPE effect, which in turn decreases the transistor gain:

As you increase the device edge spacing, then the WPE effect reduces and your design will meet the expected gain.

As your IC design is implemented these LDE effects arise, so you need a methodology that can incrementally create layout and show the LDE consequence of device spacing and placement concurrent with the design process. This requires that you use Schematic Driven Layout (SDL).

You can use both Pcells and MODGEN (module generators) to create this incremental IC layout. A circuit designer can even get a heads up before IC layout by running a sensitivity analysis on a netlist to identify which devices need to be placed farther away from the well, so expect to see this methodology in the 6.16 release in mid-2013.

The Circuit Prospector will let you define how devices should be constrained in the layout implementation to create quick, prototype layouts in order to understand LDE effects quickly.

TSMC has a fully-qualified PVS (Physical Verification System) for both 28nm and 20nm nodes, so this is used to analyze the LDE parameters extracted for each circuit.

Alan did a demo using a two-stage op-amp block. First was sensitivity analysis under both AC and transient conditions, looking at WPE and LOD effects:

Each device has four parameters for WPE and two parameters for LOD, so each parameter is swept across a range to simulate placement effects. The analysis results show us which devices in our netlist are most susceptible to LDE effects and orders them by rank:

Now I know which MOS devices are most susceptible in my design to WPE and LOD effects: M6, M1

With Circuit Prospector I find devices that should be matched, current mirrors, symmetry, etc. This helps me write layout constraints for my MODGENs. Parameters for a MODGEN were viewed and then you can quickly extract layout parasitics, creating a more accurate netlist for simulation.

A current mirror was then placed, a guard ring added, and spacing increased to reduce WPE effects. Even without routing or full MOS device placement we start to get critical feedback on circuit performance. LDE effects were measured and a plot showing the relationship between current and layout distance:

A guard ring was added and the LDE effects were reduced. This methodology gives us a real time approach to getting early layout effects into our design process.

Summary
IC design and layout at 20nm is possible by using an incremental layout approach.

Future Areas
Monte-Carlo analysis and LDE.

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