How ST Designs with Layout Dependent Effects (LDE)

How ST Designs with Layout Dependent Effects (LDE)
by Daniel Payne on 10-15-2014 at 12:00 am

I first visited STat their Agrate, Italy site where Flash memory development is done. At DACthis year Antonio Bogani talked about how ST designs with LDE while using EDA tools and a PDK (Process Design Kit) from Cadence. They recorded the 17 minute presentation, and you can view it herewithout having to register. Antonio’s… Read More


Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John StabenowRead More


Variation-aware IC Design

Variation-aware IC Design
by Daniel Payne on 04-15-2013 at 4:18 pm

We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, … Read More


When the lines on the roadmap get closer together

When the lines on the roadmap get closer together
by Don Dingee on 02-28-2013 at 12:53 pm

Tech aficionados love roadmaps. The confidence a roadmap instills – whether using tangible evidence or just a good story – can be priceless. Decisions on “the next big thing”, sometimes years and a lot of uncertain advancements away, hinge on the ability of a technology marketing team to define and communicate a roadmap.

Any roadmap… Read More


Cadence at 20nm

Cadence at 20nm
by Paul McLellan on 08-21-2012 at 8:10 pm

Cadence has a new white paper out about the changes in IC design that are coming at 20nm. One thing is very clear: 20nm is not simply “more of the same”. All design, from basic standard cells up to huge SoCs has several new challenges to go along with all the old ones that we had at 45nm and 28nm.

I should emphasize that the paper… Read More


TSMC Theater Presentation: Ciranova!

TSMC Theater Presentation: Ciranova!
by Daniel Nenni on 06-14-2012 at 9:00 pm

Ciranova presented a hierarchical custom layout flow used on several large advanced-node designs to reduce total layout time by about 50%. Ciranova itself does automated floorplanning and placement software with only limited routing; but since the first two constitute the majority of custom layout time, and strongly influence… Read More


A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design

A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design
by Eric Filseth on 04-29-2012 at 9:00 pm

At 28nm and below, a number of electrical variation effects become significant which depend not only on individual devices, but the physical interaction between neighboring devices, wells, etc during the manufacturing process. Some of these effects have become collectively referred to as “Layout Dependent Effects” (LDE);… Read More


iLVS: Improving LVS Usability at Advanced Nodes

iLVS: Improving LVS Usability at Advanced Nodes
by glforte on 12-13-2011 at 4:54 pm

LVS Challenges at Advanced Nodes

Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. As the number of layers and layer derivations increases the complexity of devices, especially Layout Dependent… Read More