Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.
Impact of IC layout design is growing greatly with new process nodes, so makes the circuit design job tougher.
Must have LVS/DRC clean design to simulate, now with 6.1.6 release you can simulate with parasitcs quicker. Use virtuoso schematic, testbench and design in one db.
Dave Styles demo – new real time extractor is now out in production, Broadcom is using it wrote about it at CDN Live.
Start simulation before LVS clean.
Used by both circuit and layout designer.
Demo of LDE on circuit simulation effects. Started with a two-stage diff amp.
FIrst simulation is schematic only, no parasitics. With M all of the LDE is applied equially to each device, lulled into a sense of false security. A Rapid Analog Placement (RAP) – creates a placed layout quickly, now the netlist has all individual devices with their own stress factors (only a handful of clicks to setup auto placement). Re-simulation now shows more accuracy. Now some nets are assisted auto-routing for analog routing, including symmetry effects.
While routing or placement is done, an online extractor is run to save time (so not a sign-off extractor). Qualification of 28nm at TSMC (60,000 patterns), very close to sign-off.
ELectrically Aware design flow (EA).
Demo – route inputs and outputs with symmetry constraints. Set the capacitance tolerances per net, maximum value cap constraints. Now re-extract new routing. Extraction values are as fast as the intaractive ouring. 45nm generic process used in the demo.
Simulated again with LDE effects and routing completed (input, output, critical net). Parasitics added from real IC layout, each MOS device has unique LDE parameters included. Near to specs, but not meeting reqiurements yet.
With partial layout the circuit design is reducing the number of iterations required. EM issues can be identified early on in the layout process. EM violations can be quickly show on the layout (no thermal checking). IDD violations shown, more routing added, Read the current density number, change the width, meet the EM rules. Still had 4 violations on EM rules, so adding more VIas makes me EM clean.
Outputs are symmetrical, but one EM violation on an outpuut. Widedning a M2 fixes the EM violation.
Virtuoso LS EAD (upgrade to an existing Vuturoso XL seat.
Cadence is still the market leader for full-custom IC layout tools, however the competition from Synopsys and Mentor keeps all vendors improving their EDA tools.
- A Chat with John Stabenow, Virtuoso Marketing at Cadence
- How To Design a TSMC 20nm Chip with Cadence Tools