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Hybrids on BeO then, 3D-IC in silicon now

Hybrids on BeO then, 3D-IC in silicon now
by Don Dingee on 10-21-2012 at 8:10 pm

Once upon a time (since every good story begins that way), I worked on 10kg, 70 mm diameter things that leapt out of tubes and chased after airplanes and helicopters. The electronics for these things were fairly marvelous, in the days when surface mount technology was in its infancy and having reliability problems in some situations.

One of the problems with surface mount in the early going was the coefficient of thermal expansion, or more accurately the difference in CTE between the ceramic packages needed for defense-style temperature range requirements (-55 to +125C), and that of the FR-4 fiberglass most printed circuit boards were constructed from. With a few heating and cooling cycles, the ceramic packages would grow or shrink at a different rate than the board underneath them, stress the solder joints, and cause cracks or breaks. BGA, solder balls, and other fine pitch techniques were yet to be invented.

The solution for dense electronics in small places with wicked temperature extremes was hybrid microelectronic assemblies, and with some improvements in materials and process it still is today. The “for dummies” (and I resemble that remark) version:

 1) Print the circuit on a ceramic substrate. At the time, the technology for substrates was beryllium oxide, viciously toxic in particle form when inhaled, but quite safe made into non-porous substrates. (One designer I worked with had a BeO coffee mug he drank from everyday to prove the point.) BeO also has super high thermal conductivity, providing a conduction cooling path. Today, you’re more likely to find aluminum nitride (AlN) in use.

2) Drop chips in raw die form onto the substrate in their proper locations.

3) Bond the pads on each chip to the corresponding pads on the substrate with thin gold wires – pretty much the same thing done inside a single IC package, except on a much larger scale with a lot of various dies and connections.

4) Put the finished circuit substrate into a Kovar metallic case, with I/O pins, and seal the edge with a weld so it’s hermetic.

5) Solder several hybrids to a flex harness providing interconnects between hybrids and connectors to other subsystems to make up the final assembly.

The lesson from electronics history is good ideas don’t go away when they are supplanted by innovation; they come back when a similar problem arises again on a smaller scale.

The idea of 3D-IC has been percolating for some time, and it’s the modern version of hybrids. The scale and materials are different, but as the TSMC name suggests – CoWoS, chip on wafer on substrate – it’s the same concept, minus wires and metal cases, and implemented completely in an EDA flow. This isn’t just to get more stuff in less space by better utilizing the Z axis, as the 3D name would imply. It’s about using the right process for the right function. Using silicon micro-bumping and through-silicon vias (TSVs) , a complete subsystem in proven silicon can be installed on a newly designed piece of 20nm digital logic. The EDA breakthrough will be making that a smooth flow instead of manual design and extra process steps.

With all the chatter about 28nm, 20nm, 14nm, and beyond, many folks might have lost sight that analog processes are no where near those geometries, and they don’t need to be. They are built out on mature, low risk, low noise process nodes. While analog is obviously involved in A/D and D/A converters, there are also MEMS sensors, and networking PHYs, and wafer-scale cameras and microphones that can all take advantage of a 3D process, without having to be redesigned into a cutting-edge geometry. Sematech summarized this nicely:

Memory subsystems are also becoming decidedly more analog in their signaling characteristics as speeds increase. Our Eric Esteve wrote earlier in a post discussing Cadence’s JEDEC Wide I/O mobile DRAM IP, and its target of 100Gbit/sec of DRAM bandwidth. Taiwan’s Industrial Technology Research Institute (ITRI) and TSMC both recently reported working with Cadence to tape out Wide I/O designs and prove out the new CoWoS flow.

If you missed the first round of hybrids, the idea is back, and it’s all in silicon this time. 3D-IC opens up a whole new range of possibilities for SoC design, not unlike what we’ve already seen at the microcontroller level on less aggressive process nodes with integrated mixed-signal EDA flow. The microcontroller-on-steroids with a much faster digital core, memory subsystems, and multiple analog I/O systems quickly and completely blending mature analog process nodes with advanced digital nodes is close at hand.

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