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PathFinder webinar: Full-chip ESD Integrity and Macro-level Dynamic ESD

PathFinder webinar: Full-chip ESD Integrity and Macro-level Dynamic ESD
by Paul McLellan on 08-01-2011 at 10:00 am

 The PathFinder webinar will be at 11am Pacific time on Thursday 4th August. It will be conducted by Karthik Srinivasan, Senior Applications Engineer at Apache Design Solutions. Mr. Srinivasan has over four years of experience in the EDA industry, focusing on die, system, and cross-domain analysis. His professional interests include power and signal integrity, reliability and low-power design. He holds a MSEE from the State University of New York, Buffalo.

The industry’s first comprehensive layout-based electrostatic discharge (ESD) integrity solution provides integrated modeling, extraction, and simulation capabilities to enable automated and exhaustive analysis of the entire IC, highlighting areas of weaknesses that can be susceptible to ESD induced failure. PathFinder also delivers innovative transistor-level dynamic ESD capabilities for validation of I/Os, analog, and mixed-signal designs.

Register for the webinar here.


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